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參數(shù)資料
型號(hào)： AD9866CHIPS
廠商： ANALOG DEVICES INC
元件分類(lèi)： 通信及網(wǎng)絡(luò)
英文描述： Broadband Modem Mixed Signal Front End
中文描述： SPECIALTY TELECOM CIRCUIT, UUC
文件頁(yè)數(shù)： 43/48頁(yè)
文件大小： 1647K
代理商： AD9866CHIPS
AD9866
A hardware
reset can be triggered by pulsing the RESET pin low
for a minimum of 50 ns. The SPI registers are instantly reset to
their default settings upon RESET going low, while the dc offset
calibration and filter tuning routine is initiated upon RESET
returning high. To ensure sufficient power-on time of the
various functional blocks, RESET returning high should occur
no less than 10 ms upon power-up. If a digital reset signal from
a microprocessor reset circuit (such as ADM1818) is not
available, a simple R-C network referenced to DVDD can be
used to hold RESET low for approximately 10 ms upon
power-up.
Rev. 0 | Page 43 of 48
ANALOG AND DIGITAL LOOP-BACK TEST MODES
The AD9866 features analog and digital loop-back capabilities
that can assist in system debug and final test. Analog loop-back
routes the digital output of the ADC back into the Tx data path
prior to the interpolation filters such that the Rx input signal
can be monitored at the output of the TxDAC or IAMP. As a
result, the analog loop-back feature can be used for a half- or
full-duplex interface, to allow testing of the functionality of the
entire IC (excluding the digital data interface).
For example, the user can configure the AD9866 with similar
settings as the target system, inject an input signal (sinusoidal
waveform) into the Rx input, and monitor the quality of the
reconstructed output from the TxDAC or IAMP to ensure a
minimum level of performance. In this test, the user can also
exercise the RxPGA as well as validate the attenuation charac-
teristics of the RxLPF. Note that the RxPGA gain setting should
be selected such that the input does not result in clipping of the
ADC.
Digital loop-back can be used to test the full-duplex digital
interface of the AD9866. In this test, data appearing on the
Tx[5:0] port is routed back to the Rx[5:0] port, thereby
confirming proper bus operation. The Rx port can also be
three-stated for half- and full-duplex interfaces.
Table 26. SPI Registers for Test Modes
Address (Hex)
Bit
0x0D
(7)
(6)
(5)
Description
Analog loop-back
Digital loop-back
Rx port three-state
相關(guān)PDF資料
PDF描述
AD9866 Broadband Modem Mixed Signal Front End
AD9866-EB Broadband Modem Mixed Signal Front End
AD9866BCP Broadband Modem Mixed Signal Front End
AD9870 IF Digitizing Subsystem
AD9870EB IF Digitizing Subsystem
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9866-EB 制造商:Analog Devices 功能描述: 制造商:Analog Devices 功能描述:12B MXFE CONVERTER FOR BROADBAND MODEMS - Bulk
AD9867 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:Broadband Modem Mixed-Signal Front End
AD9867BCPZ 功能描述:IC MXFE 75MSPS FOR TX/RX 64LFCSP RoHS:是 類(lèi)別:RF/IF 和 RFID >> RF 前端 (LNA + PA) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:250 系列:- RF 型:GPS 頻率:1575.42MHz 特點(diǎn):- 封裝/外殼:48-TQFP 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:48-TQFP 裸露焊盤(pán)（7x7） 包裝:托盤(pán)
AD9867BCPZRL 功能描述:IC MXFE 75MSPS FOR TX/RX 64LFCSP RoHS:是 類(lèi)別:RF/IF 和 RFID >> RF 前端 (LNA + PA) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:250 系列:- RF 型:GPS 頻率:1575.42MHz 特點(diǎn):- 封裝/外殼:48-TQFP 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:48-TQFP 裸露焊盤(pán)（7x7） 包裝:托盤(pán)
AD9867-EBZ 制造商:Analog Devices 功能描述:12B MXFE CONVERTER FOR BROADBAND MODEMS - Bulk
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