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參數資料
型號: AD9866CHIPS
廠商: ANALOG DEVICES INC
元件分類: 通信及網絡
英文描述: Broadband Modem Mixed Signal Front End
中文描述: SPECIALTY TELECOM CIRCUIT, UUC
文件頁數: 6/48頁
文件大小: 1647K
代理商: AD9866CHIPS
AD9866
Parameter
Rx Mode
I
AVDD
+ I
CLKVDD
I
DVDD
+ I
DRVDD
POWER CONSUMPTION OF FUNCTIONAL BLOCKS
1
(I
AVDD
+ I
CLKVDD
)
RxPGA and LPF
ADC
TxDAC
IAMP (Programmable)
Reference
CLK PLL and Synthesizer
MAXIMUM ALLOWABLE POWER DISSIPATION
STANDBY POWER CONSUMPTION
IS_TOTAL (Total Supply Current)
POWER DOWN DELAY (USING PWR_DWN PIN)
RxPGA and LPF
ADC
TxDAC
IAMP
CLK PLL and Synthesizer
POWER UP DELAY (USING PWR_DWN PIN)
RxPGA and LPF
ADC
TxDAC
IAMP
CLK PLL and Synthesizer
1
Default power-up settings for MODE = HIGH and CONFIG = LOW, IOUTP_FS = 20 mA, does not include IAMP’s current consumption, which is application dependent.
2
Default power-up settings for MODE = LOW and CONFIG = LOW .
Rev. 0 | Page 6 of 48
Temp
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
Full
Full
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
Test Level
III
III
III
III
III
III
IV
III
III
III
III
III
III
III
III
III
III
Min
10
Typ
225
36.5
87
108
38
170
107
13
440
12
20
20
27
7.8
88
13
20
20
Max
253
39
120
1.66
Unit
mA
mA
mA
mA
mA
mA
mA
mA
W
mA
ns
ns
ns
ns
ns
μs
ns
μs
ns
μs
DIGITAL SPECIFICATIONS
Table 4. AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%; R
SET
= 2 k, unless otherwise noted
Parameter
CMOS LOGIC INPUTS
High Level Input Voltage
Low Level Input Voltage
Input Leakage Current
Input Capacitance
CMOS LOGIC OUTPUTS (C
LOAD
= 5 pF)
High Level Output Voltage (I
OH
= 1 mA)
Low Level Output Voltage (I
OH
= 1 mA)
Output Rise/Fall Time (High Strength Mode and C
LOAD
= 15 pF)
Output Rise/Fall Time (Low Strength Mode and C
LOAD
= 15 pF)
Output Rise/Fall Time (High Strength Mode and C
LOAD
= 5 pF)
Output Rise/Fall Time (Low Strength Mode and C
LOAD
= 5 pF)
RESET
Minimum Low Pulse Width (Relative to f
ADC
)
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Test Level
VI
VI
VI
VI
VI
VI
VI
VI
VI
Min
DRVDD – 0.7
DRVDD – 0.7
1.2
1
Typ
3
2
1.5/2.3
1.9/2.7
0.7/0.7
1.0/1.0
Max
0.4
12
Unit
V
V
μA
pF
ns
ns
ns
ns
Clock
cycles
相關PDF資料
PDF描述
AD9866 Broadband Modem Mixed Signal Front End
AD9866-EB Broadband Modem Mixed Signal Front End
AD9866BCP Broadband Modem Mixed Signal Front End
AD9870 IF Digitizing Subsystem
AD9870EB IF Digitizing Subsystem
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參數描述
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