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參數資料
| 型號： | AD9873JS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網絡 |
| 英文描述： | Analog Front End Converter for Set-Top Box, Cable Modem |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP100 |
| 封裝： | METRIC, QFP-100 |
| 文件頁數： | 12/39頁 |
| 文件大小： | 935K |
| 代理商： | AD9873JS |
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REV. 0
AD9873
–12–
REGISTER BIT DEFINITIONS
00h, Bits 0–4: OSC IN Multiplier–Register Address
This register field is used to program the on-chip multiplier (PLL)
that generates the chip’s high-frequency system clock, f
SYSCLK
.
For example, to multiply the external crystal clock f
OSCIN
by 19
decimal, program register address 00h, Bits 5–1 as 13h. Default
value is M = 16 = 10h. Valid entries range from M = 1 to 31.
M = 1 (no PLL) requires a very stable, high-frequency clock at
OSC IN. A changed f
SYSCLK
frequency is stable (PLL locked)
after a maximum of 200 f
MCLK
cycles (= Wake-Up Time).
00h, Bit 5:
RESET
Writing a one to this bit resets the registers to their default val-
ues and restarts the chip. The
RESET
bit always reads back
0. Register address 00h bits are not cleared by this software reset.
However, a low level at the
RESET
pin would force all registers,
including all bits in address 00h, to their default state.
00h, Bit 6: LSB/MSB First
Active high indicates SPI serial port access of instruction byte
and data registers is least significant bit (LSB) first. Default low
indicates most significant bit (MSB) first format.
00h, Bit 7: SDIO Bidirectional
Default low indicates SPI serial port uses dedicated input/output
lines (SDIO and SDO pin). High configures serial port as single
line I/O (SDIO pin is used bidirectional).
01h, Bits 0–5: MCLK Divider
This register is used to divide the chip’s master clock by R, where
R is an integer between 2 and 63. The generated reference clock,
REF CLK, can be used for external frequency-controlled
devices. Default value is R = 9.
01h, Bit 6: OSC IN Divider
The OSC IN multiplier output clock can be divided by 4 or 3 to
generate the chip’s master clock. Active high indicates a divide
ratio of N = 3. Default low configures a divide ratio of N = 4.
01h, Bit 7: PLL Lock Detect
If this bit is set to 1, REF CLK pin is disabled from the nor-
mal usage. In this mode REF CLK high signals that the internal
phase lock loop (PLL) is in lock with CLK IN.
02h Bits 0–7: Power-Down
Sections of the chip that are not used can be put in a power saving
mode when the corresponding bits are set to 1. This register has
a default value of 00h with all sections active.
Bit 0: Power-Down 8-bit ADC powers down the 8-bit ADC
and stops RxSYNC framing signal.
Bit 1: Power-Down 10-bit ADC reference powers down the
internal 10-bit ADC reference.
Bit 2: Power-Down 10-bit ADC powers down the 10-bit ADC.
Bit 3: Power-Down 12-bit ADC reference powers down the
internal 12-bit ADC reference.
Bit 4: Power-Down 12-bit ADC powers down the 12-bit ADC.
Bit 5: Power-Down Tx powers down the transmit section of
the chip.
Bit 6: Power-Down DAC Tx powers down the DAC.
Bit 7: Power-Down PLL powers down the CLK IN Multiplier.
03h to 06h: Sigma-Delta Output Control Words
The Sigma-Delta Output Control Words –0 and –1 are 12 bits
wide and split in MSB bits <11:4> and LSB bits <3:0>. Changes
to the sigma-delta outputs take effect immediately for every MSB
or LSB register write. Sigma-delta output control words have a
default value of 0. The smaller the programmed values in these
registers, the lower are the integrated (low-pass filtered) sigma
delta output levels (straight binary format).
07h, Bits 0–6: Clamp Level Control for Video Input
A 7-bit clamp level offset can be set for the internal automatic
clamp level control loop of the Video Input.
Clamp level offset = Clamp level control
×
16.
This register defaults to 32 = 20h, which amounts to a clamp
level offset of 512 LSB = 200h. Valid clamp level control values
are 16 to 127.
07h, Bit 7: Video Input Enable
This bit controls the multiplexer to the 12-bit ADC and deter-
mines if IF12 input or Video input is used. The bit is default set
to 0 for the IF12 input.
08h, Bit 0: Test 10-Bit ADC
Active high allows nonmultiplexed 10-bit ADC data only to be
read at IF outputs. Output data changes at half MCLK clock rate.
This bit defaults to 0.
08h, Bit 1: Test 12-Bit ADC
Active high allows nonmultiplexed 12-bit ADC data only to be
read at IF outputs. Output data changes at half MCLK clock rate.
This bit defaults to 0.
08h, Bit 5 and Bit 7: ADC Clock Select
Active high indicates that the frequency at OSC IN is directly used
to sample the on chip ADCs. Default low indicates that the on
chip ADCs generate their sampling frequencies from the internally
generated master clock MCLK. Both Bit 5 and Bit 7 need to be
programmed with the same values.
0Ch, Bits 0–3: Version
This register stores the die version of the chip. It can only be read.
0Fh, Bit 0: Single-Tone Tx Mode
Active high configures the AD9873 for single-tone applications.
The AD9873 will supply a single frequency output as determined
by the frequency tuning word (FTW) selected by the active
profile. In this mode, the Tx IQ input data pins are ignored
but should be tied high or low. Default value of single-tone
Tx mode is 0 (inactive).
0Fh, Bit 1: Spectral Inversion Tx
When set to 1, inverted modulation is performed
(I
cos
(
ω
t
) + Q
sin
(
ω
t
)).
Default is logic zero, noninverted modulation
(I
cos
(
ω
t
) – Q
sin
(
ω
t
)).
0Fh, Bit 2: Bypass Inv Sinc Tx Filter
Active high, configures the AD9873 to bypass the SIN(X)/X
compensation filter. Default value is 0 (inverse sinc filter enabled).
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相關代理商/技術參數 |
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|---|---|
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| AD9874ABST | 制造商:Analog Devices 功能描述:IC IF DIG SUBSYSTEM |
| AD9874ABSTRL | 功能描述:IC IF DIGIT SUBSYSTEM 48-LQFP RoHS:否 類別:RF/IF 和 RFID >> RF 其它 IC 和模塊 系列:- 標準包裝:100 系列:* |
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