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參數資料
| 型號： | AD9873JS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網絡 |
| 英文描述： | Analog Front End Converter for Set-Top Box, Cable Modem |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP100 |
| 封裝： | METRIC, QFP-100 |
| 文件頁數： | 28/39頁 |
| 文件大小： | 935K |
| 代理商： | AD9873JS |
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REV. 0
AD9873
–28–
X
Q
I
Z
X
Figure 13. 16-Quadrature Modulation
Tx Signal Level Considerations
The quadrature modulator itself introduces a maximum gain of
3 dB in signal level. To visualize this, assume that both the I data
and Q data are fixed at the maximum possible digital value, x.
Then the output of the modulator, z, is:
z
= [
x
cos
(
ω
t
)
–
x sin
(
ω
t
)]
It can be shown that
z
assumes a maximum value of
(
z
number of bits were used to represent the
z
values, as is used to
represent the x values, an overflow would occur. To prevent this
possibility, an effective
–
3 dB attenuation is internally imple-
mented on the I and Q data path.
x
x
x
=
+
)
=
2
2
2
(a gain of +3 dB). However, if the same
z
x
=
(
)
=
1 2 1 2
/
/
The following example assumes a Pk/rms level of 10 dB:
Maximum Symbol Component Input Value
=
(2047
LSBs
–
0.2
dB
) = 2000
LSBs
Maximum Complex Input rms Value
=
2000
LSBs
+ 6
dB
–
Pk/rms
(
dB
) = 1265
LSBs rms
Maximum Complex Input
rms Value
calculation uses both I and
Q symbol components which adds a factor of 2 (= 6 dB) to
the formula.
Table IV. I–Q Input Test Signals
Input Level
Modulator Output Level
Single-Tone (fc
–
f)
I = cos(f)
Q = cos(f + 90 ) =
–
sin(f)
I = cos(f)
Q = cos(f + 270 ) = sin(f)
I = cos(f)
Q = cos(f + 180 ) =
–
cos(f) or Q = cos(f)
FS
–
0.2 dB
FS
–
0.2 dB
FS
–
0.2 dB
FS
–
0.2 dB
FS
–
0.2 dB
FS
–
0.2 dB
FS
–
3.0 dB
Single-Tone (fc + f)
FS
–
3.0 dB
Dual-Tone (fc
f)
FS
If INV SINC filter is enabled, an insertion loss of ~1.4dB (for low
frequencies) occurs at the DAC output (see Figure 12a, 12b).
Programming the AD9873 to single-tone transmit mode while
disabling the INV SINC filter (address 0Fh) generates a maximum
(FS) amplitude single tone with a frequency (fc) determined by
the associated frequency tuning word.
Table IV shows typical I
–
Q input test signals with amplitude levels
related to 12-bit full scale (FS).
Tx Throughput and Latency
Data inputs effect the output fairly quickly but remain effective
due to AD9873
’
s filter characteristics. Data transmit latency
through the AD9873 is easiest to describe in terms of f
SYSCLK
clock cycles (4 f
MCLK
). The numbers quoted are when an effect
is first seen after an input value change.
Latency of I/Q data entering the data assembler (AD9873 input)
to the DAC output is 119 f
SYSCLK
clock cycles (29.75 f
MCLK
cycles). DC values applied to the data assembler input will take
up to 176 f
SYSCLK
clock cycles (44 f
MCLK
cycles) to propagate and
settle at the DAC output. Enabling the Inverse SINC Filter adds
only 2 f
SYSCLK
clock cycles latency.
Frequency hopping is accomplished via changing the PROFILE
input pins. The time required to switch from one frequency
to another is less than 234 f
SYSCLK
cycles with the Inverse SINC
Filter engaged. With the Inverse SINC Filter bypassed, the
latency drops to less than 232 f
SYSCLK
cycles (58.5 f
MCLK
cycles).
D/A Converter
A 12-bit digital-to-analog converter (DAC) is used to convert
the digitally processed waveform into an analog signal. The worst-
case spurious signals due to the DAC are the harmonics of the
fundamental signal and their aliases. (Please see the AD9851 data
sheet for a detailed explanation of aliased images.) The wideband
12-bit DAC in the AD9873 maintains spurious-free dynamic
range (SFDR) performance of 59 dBc up to f
OUT
= 42 MHz
and 54 dBc up to f
OUT
= 65 MHz. The conversion process will
produce aliased components of the fundamental signal at n
f
SYSCLK
f
CARRIER
(n = 1, 2, 3). These are typically filtered with
an external RLC filter at the DAC output. It is important for
DAC
INV
SINC
FILTER
0dB
1.4dB
12
HBF + CIC
INTERPOLATOR
+0.2dB
HBF + CIC
INTERPOLATOR
+0.2dB
ATTENUATOR
–
3dB
MODULATOR
3dB MAX
I
O
O
I
12
12
I
O
COMPLEX
DATA
INPUT
ATTENUATOR
–
3dB
TWO'S COMPLEMENT FORMAT
Figure 14. Signal Level Contribution
相關PDF資料 |
PDF描述 |
|---|---|
| AD9874 | IF Digitizing Subsystem |
| AD9874BST | IF Digitizing Subsystem |
| AD9874EB | IF Digitizing Subsystem |
| AD9875BSTRL | Broadband Modem Mixed-Signal Front End |
| AD9875 | Broadband Modem Mixed-Signal Front End |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9874 | 制造商:AD 制造商全稱:Analog Devices 功能描述:IF Digitizing Subsystem |
| AD9874ABST | 功能描述:IC IF DIGIT SUBSYSTEM 48-LQFP RoHS:否 類別:RF/IF 和 RFID >> RF 其它 IC 和模塊 系列:- 標準包裝:100 系列:* |
| AD9874ABST | 制造商:Analog Devices 功能描述:IF DIGITIZING SYBSYSTEM ((NW)) 制造商:Analog Devices 功能描述:IC, IF DIGITIZING SUBSYSTEM, LQFP-48 |
| AD9874ABST | 制造商:Analog Devices 功能描述:IC IF DIG SUBSYSTEM |
| AD9874ABSTRL | 功能描述:IC IF DIGIT SUBSYSTEM 48-LQFP RoHS:否 類別:RF/IF 和 RFID >> RF 其它 IC 和模塊 系列:- 標準包裝:100 系列:* |
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