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參數(shù)資料
| 型號(hào)： | AD9873JS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Analog Front End Converter for Set-Top Box, Cable Modem |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP100 |
| 封裝： | METRIC, QFP-100 |
| 文件頁數(shù)： | 21/39頁 |
| 文件大小： | 935K |
| 代理商： | AD9873JS |
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REV. 0
AD9873
–21–
Single-Tone Output Transmit Operation
The AD9873 can be configured for frequency synthesis applica-
tions by writing the single-tone bit true, and applying a clock signal
(e.g., Rx SYNC) to the Tx SYNC pin. In single-tone mode, the
AD9873 disengages the modulator and preceding data path
logic to output a spectrally pure single frequency sine wave. The
AD9873 provides for a 24-bit frequency tuning word, which
results in a tuning resolution of 12.9 Hz at a f
SYSCLK
rate of
216 MHz. A good rule of thumb when using the AD9873 as a
frequency synthesizer is to limit the fundamental output frequency
to 30% of f
SYSCLK
. This avoids generating aliases too close to the
desired fundamental output frequency, thus minimizing the cost
of filtering the aliases.
All applicable programming features of the AD9873 apply when
configured in single-tone mode. These features include:
1. Frequency hopping via the PROFILE inputs and associated
tuning word, which allows Frequency Shift Keying (FSK)
modulation.
2. Ability to bypass the SIN(x)/x compensation filter.
3. Power-down modes.
OSC IN Clock Multiplier
As mentioned earlier, the output data is sampled at the rate
of f
SYSCLK
. Since the AD9873 is designed to operate at f
SYSCLK
frequencies up to 232 MHz, there is the potential difficulty of
trying to provide a stable input clock f
OSCIN
. Although stable,
high-frequency oscillators are available commercially, they tend
to be cost prohibitive and create noise coupling issues on the
printed circuit board. To alleviate this problem, the AD9873
has a built-in programmable clock multiplier and an oscillator
circuit. This allows the use of a relatively low frequency (thus,
less expensive) crystal or oscillator to generate the OSC IN
signal. The low frequency OSC IN signal can then be multiplied
in frequency by an integer factor of between 1 and 31, inclusive,
to become the f
SYSCLK
clock.
For DDS applications, the carrier is typically limited to about 30%
of f
SYSCLK
. For a 65 MHz carrier, the recommended system
clock is above 216 MHz.
The OSC IN Multiplier function maintains clock integrity as
evidenced by the AD9873’s system phase noise characteristics
of –113 dBc/Hz. External loop filter components consisting of a
series resistor (1.3
k
) and capacitor (0.01
compensation zero for the CLK IN Multiplier PLL loop. The
overall loop performance has been optimized for these compo-
nent values.
Receive Section
The AD9873 includes four high-speed, high-performance ADCs.
Two matched 8-bit ADCs are optimized for analog IQ demodu-
lated signals and can be sampled with up to 16.5MSPS. A direct
IF 10-bit ADC and a 12-bit ADC can digitize signals at a maxi-
mum sampling frequency of 33 MSPS. Input signal selection to
the 12-bit ADC can be programmed to either direct IF or video
(NTSC/PAL). A programmable automatic clamp control pro-
vides black level offset correction for video signals.
The ADC sampling frequency can either be derived directly from
the OSC IN crystal or from the on-chip OSC IN Multiplier.
For highest dynamic performance it is recommended to choose a
OSC IN frequency that can be used to directly sample the ADCs.
F) provide the
Transmit Section
Modulation Mode Operation
The AD9873 accepts 6-bit words, which are strobed synchronous
to the master clock MCLK into the Data Assembler. Tx SYNC
signals the start of a transmit symbol. Two successive 6-bit words
form a 12-bit symbol component. The incoming data is assumed
to be complex, in that alternating 12-bit words are regarded as the
inphase (I) and quadrature (Q) components of a symbol. Symbol
components are assumed to be in two’s complement format.
The rate at which the 6-bit words are presented to the AD9873
will be referred to as the master clock rate (f
MCLK
). The Data
Assembler splits the incoming data words into separate I/Q data
streams. The rate at which the I/Q data word pairs appear at the
output of the Data Assembler will be referred to as the I/Q Sample
Rate (f
IQCLK
). Since two 6-bit input data words are used to con-
struct each individual I and Q data paths, it should be apparent
that the input 6-bit data rate f
MCLK
is four times the I/Q sample
rate (f
MCLK
= 4 f
IQCLK
).
Once through the Data Assembler, the I/Q data streams are fed
through two half-band filters (half-band filters #1 and #2). The
combination of these two filters results in a factor of four (4)
increase of the sample rate. Thus, at the output of half-band
filter #2, the sample rate is 4 f
IQCLK
. In addition to the sample
rate increase, the half-band filters provide the low-pass filtering
characteristic necessary to suppress the spectral images produced
by the upsampling process.
After passing through the half-band filter stages, the I/Q data
streams are fed to a Cascaded Integrator-Comb (CIC) filter. This
filter is configured as an interpolating filter, which allows further
upsampling rates of 3 or 4. The CIC filter, like the half-bands, has
a built-in low-pass characteristic. Again, this provides for suppres-
sion of the spectral images produced by the upsampling process.
The digital quadrature modulator stage following the CIC filters
is used to frequency-shift the baseband spectrum of the incom-
ing data stream up to the desired carrier frequency (this process
is known as
upconversion
).
The carrier frequency is numerically controlled by a Direct Digital
Synthesizer (DDS). The DDS uses its internal reference clock
(f
SYSCLK
) to generate the desired carrier frequency with a high
degree of precision. The carrier is applied to the I and Q multi-
pliers in quadrature fashion (90
phase offset) and summed to yield
a data stream that is at the modulated carrier.
It should be noted at this point that the incoming symbols have
been converted from an input sample rate of f
IQCLK
to an output
sample rate of f
SYSCLK
(see Figure 1). The modulated carrier is
ultimately destined to serve as the input to the digital-to-analog
converter (DAC) integrated on the AD9873.
The DAC output spectrum is distorted due to the intrinsic zero-
order hold effect associated with DAC-generated signals. This
distortion is deterministic and follows the familiar SIN(X)/X
(or SINC) envelope. Since the SINC distortion is predictable, it is
also correctable. Hence, the presence of the optional Inverse
SINC Filter preceding the DAC. This is a FIR filter, which has
a transfer function conforming to the inverse of the SINC
response. Thus, when selected, it modifies the incoming data
stream so that the SINC distortion, which would otherwise
appear in the DAC output spectrum, is virtually eliminated.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9874 | IF Digitizing Subsystem |
| AD9874BST | IF Digitizing Subsystem |
| AD9874EB | IF Digitizing Subsystem |
| AD9875BSTRL | Broadband Modem Mixed-Signal Front End |
| AD9875 | Broadband Modem Mixed-Signal Front End |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9874 | 制造商:AD 制造商全稱:Analog Devices 功能描述:IF Digitizing Subsystem |
| AD9874ABST | 功能描述:IC IF DIGIT SUBSYSTEM 48-LQFP RoHS:否 類別:RF/IF 和 RFID >> RF 其它 IC 和模塊 系列:- 標(biāo)準(zhǔn)包裝:100 系列:* |
| AD9874ABST | 制造商:Analog Devices 功能描述:IF DIGITIZING SYBSYSTEM ((NW)) 制造商:Analog Devices 功能描述:IC, IF DIGITIZING SUBSYSTEM, LQFP-48 |
| AD9874ABST | 制造商:Analog Devices 功能描述:IC IF DIG SUBSYSTEM |
| AD9874ABSTRL | 功能描述:IC IF DIGIT SUBSYSTEM 48-LQFP RoHS:否 類別:RF/IF 和 RFID >> RF 其它 IC 和模塊 系列:- 標(biāo)準(zhǔn)包裝:100 系列:* |
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