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參數資料
| 型號： | AD9873JS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網絡 |
| 英文描述： | Analog Front End Converter for Set-Top Box, Cable Modem |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP100 |
| 封裝： | METRIC, QFP-100 |
| 文件頁數： | 22/39頁 |
| 文件大小： | 935K |
| 代理商： | AD9873JS |
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REV. 0
AD9873
–22–
Digital 8-bit ADC outputs are multiplexed to one 4-bit bus,
clocked by a frequency (f
MCLK
) of four times the sampling rate
whereas the 10- and 12-bit ADCs are multiplexed together
to one 12-bit bus clocked by f
MCLK,
which is two times their
sampling frequency.
CLOCK AND OSCILLATOR CIRCUITRY
The AD9873’s internal oscillator generates all sampling clocks
from a simple, low-cost, series resonance, fundamental frequency
quartz crystal. Figure 2 shows how the quartz crystal is connected
between OSC IN (Pin 61) and XTAL (Pin 60) with parallel
resonant load capacitors as specified by the crystal manufacturer.
The internal oscillator circuitry can also be overdriven by a TTL
level clock applied to OSC IN with XTAL left unconnected.
f
OSC IN
=
f
MCLK
×
N
/
M
An internal phase locked loop (PLL) generates the DAC sampling
frequency f
SYSCLK
by multiplying OSC IN frequency M times
(register address 00h). The MCLK signal (Pin 23) f
MCLK
is
derived by dividing this PLL output frequency with the interpo-
lation rate N of the CIC filter stages (register address 01h).
f
SYSCLK
=
f
OSC IN
×
M
f
MCLK
=
f
OSC IN
×
M
/
N
An external PLL loop filter (Pin 57) consisting of a series resistor
and ceramic capacitor (Figure 15, R1 = 1.3k
, C12 = 0.01
μ
F) is
required for stability of the PLL. Also, a shield surrounding these
components is recommended to minimize external noise coupling
into the PLL’s voltage controlled oscillator input (guard trace
connected to AVDD PLL).
Figure 1 shows that ADCs are either directly sampled by a low-
jitter clock at OSC IN or by a clock that is derived from the PLL
output. Operating modes can be selected in register address 08.
Sampling the ADCs directly with the OSC IN clock requires
MCLK to be programmed to be twice the OSC IN frequency.
5
6
4
3
2
7
8
9
10
1
11
12
16
17
15
14
13
18
19
20
21
22
23
24
25
26
27
28
29
30
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
4
4
5
3
3
76
75
77
78
79
74
73
72
71
70
69
80
65
64
66
67
68
63
62
61
60
59
58
57
56
55
54
53
52
51
1
9
9
9
9
9
9
9
9
9
9
8
8
8
8
8
8
8
8
8
PIN 1
IDENTIFIER
TOP VIEW
(Pins Down)
V
A
I
I
–
A
A
R
R
A
A
I
I
–
A
A
R
R
A
A
Q
Q
–
T
T
D
D
P
P
R
D
D
D
S
C
S
S
D
D
P
R
F
A
AGND IQ
I IN+
I IN
–
AGND IQ
REFT8
REFB8
AGND IQ
AVDD IQ
DRVDD
REF CLK
DRGND
DGND SO
SDELTA0
SDELTA1
DVDD SD
CA ENABLE
CA DATA
CA CLK
DVDD OSC
OS IN
XTAL
DGND OSC
AGND PLL
PLL FILTER
AVDD PLL
DVDD PLL
DGND PLL
AVDD Tx
Tx+
Tx
–
DRGND
DRVDD
(MSB)
IF(11)
IF(10)
IF(9)
IF(8)
IF(7)
IF(6)
IF(5)
IF(4)
IF(3)
IF(2)
IF(1)
IF(0)
(MSB)
Rx IQ(3)
Rx IQ(2)
Rx
IQ(1)
Rx
IQ(0)
Rx
SYNC
DRGND
DRVDD
MLCK
DVDD
DGND
Tx
SYNC
(MSB)
Tx
IQ(5)
Tx
IQ(4)
Tx
IQ(3)
Tx
IQ(2)
AD9873
AVDD
C7
0.1 F
C8
0.1 F
C9
0.1 F
CP2
10 F
C4
0.1 F
C5
0.1 F
C6
0.1 F
CP1
10 F
C1
0.1 F
C2
0.1 F
C3
0.1 F
C10
20pF
C11
20pF
R1
1.3k
CP3
10 F
C12
0.01 F
GUARD TRACE
C13
0.1 F
R
SET
10k
Figure 2. Basic Connections Diagram
相關PDF資料 |
PDF描述 |
|---|---|
| AD9874 | IF Digitizing Subsystem |
| AD9874BST | IF Digitizing Subsystem |
| AD9874EB | IF Digitizing Subsystem |
| AD9875BSTRL | Broadband Modem Mixed-Signal Front End |
| AD9875 | Broadband Modem Mixed-Signal Front End |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9874 | 制造商:AD 制造商全稱:Analog Devices 功能描述:IF Digitizing Subsystem |
| AD9874ABST | 功能描述:IC IF DIGIT SUBSYSTEM 48-LQFP RoHS:否 類別:RF/IF 和 RFID >> RF 其它 IC 和模塊 系列:- 標準包裝:100 系列:* |
| AD9874ABST | 制造商:Analog Devices 功能描述:IF DIGITIZING SYBSYSTEM ((NW)) 制造商:Analog Devices 功能描述:IC, IF DIGITIZING SUBSYSTEM, LQFP-48 |
| AD9874ABST | 制造商:Analog Devices 功能描述:IC IF DIG SUBSYSTEM |
| AD9874ABSTRL | 功能描述:IC IF DIGIT SUBSYSTEM 48-LQFP RoHS:否 類別:RF/IF 和 RFID >> RF 其它 IC 和模塊 系列:- 標準包裝:100 系列:* |
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