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參數資料
| 型號： | AD9874EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | IF Digitizing Subsystem |
| 中文描述： | 中頻數字化子系統 |
| 文件頁數： | 33/40頁 |
| 文件大小： | 744K |
| 代理商： | AD9874EB |
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REV. 0
AD9874
–33–
EXTERNAL PASSIVE COMPONENT REQUIREMENTS
Figure 26 shows an example circuit using the AD9874 while
Table XIV shows the nominal dc bias voltages seen at the different
pins. The purpose is to show the various external passive compo-
nents required by the AD9874 along with nominal dc voltages
for troubleshooting purposes.
MXOP
MXON
GNDF
IF2N
IF2P
VDDF
GCP
GCN
VDDA
GNDA
VREFP
VREFN
GNDL
FREF
GNDS
SYNCB
GNDH
FS
DOUTB
DOUTA
CLKOUT
VDDH
VDDD
PE
V
I
C
G
C
L
L
C
V
V
I
G
R
13 14 15 16 17 18 19 20 21 22 23 24
V
I
G
V
G
C
C
G
G
P
P
48 47 46 45 44 43 42 41 40 39 38 37
1
2
3
4
5
6
7
8
9
10
11
12
25
26
27
28
29
30
31
32
33
34
35
36
AD9874
50
180pF
1
1
L
100pF
100
pF
2.2nF
100pF
10nF
100pF
100k
10nF
10nF
1
1
1
1
1
1
Figure 26. Example Circuit Showing Recommended
Component Values
Table XIV. Nominal DC Bias Voltages
Pin Number
Pin Name (V)
Nominal DC Bias
1
2
4
5
11
12
13
19
20
35
41
42
43
44
46
47
MXOP
MXON
IF2N
IF2P
VREFP
VREFN
RREF
CLKP
CLKN
FREF
CXVM
LON
LOP
CXVL
CXIF
IFIN
VDDI – 0.2
VDDI – 0.2
1.3 – 1.7
1.3 – 1.7
VDDA/2 + 0.250
VDDA/2 – 0.250
1.2
VDDC – 1.3
VDDC – 1.3
VDDC/2
1.6 – 2.0
1.65 – 1.9
1.65 – 1.9
VDDI – 0.05
1.6 – 2.0
0.9 – 1.1
The LO, CLK, and IFIN signals are coupled to their respective
inputs using 10 nF capacitors. The output of the mixer is coupled
to the input of the ADC using 100 pF. An external 100 k
resistor
from the RREF Pin to GND sets up the AD9874’s internal bias
currents. VREFP and VREFN provide a differential reference
voltage to the AD9874’s - ADC and must be decoupled by
a 0.01
μ
F differential capacitor along with two 100 pF capacitors
to GND. The remaining capacitors are used to decouple other
sensitive internal nodes to GND.
Although power supply decoupling capacitors are not shown,
it is recommended that a 0.1
μ
F surface-mount capacitor be
placed as close as possible to each power supply pin for maximum
effectiveness. Also not shown is the input impedance matching
network used to match the AD9874’s IF input to the external
IF filter. Lastly, the loop filter components associated with the
LO and CLK synthesizers are not shown.
LC component values for
f
CLK
= 18 MHz are given on the diagram.
For other clock frequencies, the two inductors and the capacitor
of the LC tank should be scaled in inverse proportion to the clock.
For example, if
f
CLK
= 26 MHz, then the two inductors should
be = 6.9
μ
H and the capacitor should be about 120 pF. A toler-
ance of 10% is sufficient for these components since tuning of
the LC tank is performed upon system start-up.
APPLICATIONS
Superheterodyne Receiver Example
The AD9874 is well suited for analog and/or digital narrow-band
radio systems based on a superheterodyne receiver architecture. The
superheterodyne architecture is noted for achieving exceptional
dynamic range and selectivity by using two or more downcon-
version stages to provide amplification of the target signal while
filtering the undesired signals. The AD9874 greatly simplifies
the design of these radio systems by integrating the complete
IF strip (excluding the LO VCO) while providing an I/Q digital
output (along with other system parameters) for the demodulation
of both analog and digital modulated signals. The AD9874’s
exceptional dynamic range often simplifies the IF filtering
requirements and eliminates the need for an external AGC.
Figure 27 shows a typical dual conversion superheterodyne receiver
using the AD9874. An RF tuner is used to select and down-
convert the target signal to a suitable first IF for the AD9874.
A preselect filter may precede the tuner to limit the RF input to
the band of interest. The output of the tuner drives an IF filter
that provides partial suppression of adjacent channels and inter-
ferers that could otherwise limit the receiver’s dynamic range. The
conversion gain of the tuner should be set such that the peak IF input
signal level into the AD9874 is no greater than –18 dBm to prevent
clipping. The AD9874 downconverts the first IF signal to a second
IF that is exactly 1/8 of the - ADC’s clock rate (i.e.,
f
CLK
/8)
to simplify the digital quadrature demodulation process.
相關PDF資料 |
PDF描述 |
|---|---|
| AD9875BSTRL | Broadband Modem Mixed-Signal Front End |
| AD9875 | Broadband Modem Mixed-Signal Front End |
| AD9875-EB | Broadband Modem Mixed-Signal Front End |
| AD9875BST | Broadband Modem Mixed-Signal Front End |
| AD9876 | Broadband Modem Mixed-Signal Front End |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9874-EB | 制造商:Analog Devices 功能描述: |
| AD9874-EBZ | 功能描述:BOARD EVAL FOR AD9874 制造商:analog devices inc. 系列:- 零件狀態:有效 類型:數字轉換器 頻率:10MHz ~ 300MHz 配套使用產品/相關產品:AD9874 所含物品:板 標準包裝:1 |
| AD9875 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Broadband Modem Mixed-Signal Front End |
| AD9875BST | 制造商:Analog Devices 功能描述:Modem Chip Single 48-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:10B BROADBAND MODEM MXFE CONVERTER - Tape and Reel |
| AD9875BSTRL | 制造商:Analog Devices 功能描述:Modem Chip Single 48-Pin LQFP T/R |
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