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參數資料
| 型號： | AD9874EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | IF Digitizing Subsystem |
| 中文描述： | 中頻數字化子系統 |
| 文件頁數： | 8/40頁 |
| 文件大小： | 744K |
| 代理商： | AD9874EB |
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REV. 0
–8–
AD9874
(VDDI = VDDF = VDDA = VDDC = VDDL = VDDD = VDDH = VDDx, VDDQ = VDDP = 5.0 V, f
CLK
= 18 MSPS, f
IF
= 109.56 MHz, f
LO
= 107.4 MHz,
T
A
= 25 C, LO = –5 dBm, LO and CLK Synthesizer Disabled, 16-Bit Data with AGC and DVGA enabled, unless otherwise noted.)
1
IFIN CLIP POINT – dBm
P
100
80
60
40
20
0
–19.4 –19.2 –19.0 –18.8 –18.6 –18.4
+25 C
+85 C
–40 C
TPC 4a. CDF of Maximum VGA
Attenuation “Clip Point” (VDDx = 3.0 V,
High Bias
2
)
IFIN CLIP POINT – dBm
P
100
80
60
40
20
0
–31.6
+25 C
+85 C
–40 C
–31.4 –31.2 –31.0 –30.8 –30.6 –30.4
TPC 5a. CDF of Minimum VGA
Attenuation “Clip Point” (VDDx = 3.0 V,
High Bias
2
)
SUPPLY CURRENT – mA
P
100
80
60
40
20
0
18.5 19.0 19.5 20.0 20.5 21.0 21.5 22.0
+85 C
+25 C
–40 C
TPC 6a. CDF of Supply Current
(VDDx = 3.0 V, High Bias
2
)
VDDx – V
I
2.7
3.0
3.3
3.6
–20.5
–20.0
–19.5
–19.0
–18.5
–18.0
–17.5
–40 C
+25 C
+85 C
TPC 4b. Maximum VGA Attenuation
“Clip Point” vs. Supply (High Bias
2
)
VDDx – V
I
–29.5
2.7
3.0
3.3
3.6
+85 C
+25 C
–30.0
–30.5
–31.0
–31.5
–32.0
–40 C
TPC 5b. Minimium VGA Attenuation
“Clip Point” vs. Supply (High Bias
2
)
f
CLK
– MHz
S
16
13
14
10
6
2
0
12
8
4
15
17
19
21
23
25
DIGITAL
(IDDD, IDDC, AND IDDL)
DIGITA(IDDH)
ANALOG
(IDDA, IDDF, AND IDDI)
TPC 6b. Supply Current vs. f
CLK
(VDDx = 3.0 V, High Bias
2
)
VDDx – V
I
–17.5
2.7
3.0
3.3
3.6
–40 C
+85 C
+25 C
–18.0
–18.5
–19.0
–19.5
–20.0
–20.5
TPC 4c. Maximum VGA Attenuation
“Clip Point” vs. Supply (Low Bias
3
)
VDDx – V
I
–29.5
2.7
3.0
3.3
3.6
+85 C
+25 C
–30.0
–30.5
–31.0
–31.5
–32.0
–40 C
TPC 5c. Minimium VGA Attenuation
“Clip Point” vs. Supply (Low Bias
3
)
VDDx – V
S
18
2.7
3.0
3.3
3.6
16
12
8
4
0
DIGITAL INTERFACE
(IDDH)
(IDDD, IDIGITAL
(IDDA, ANALOG
14
10
6
2
TPC 6c. Supply Current vs. Supply
(High Bias
2
)
1
Data taken with Toko FSLM series 10
μ
H inductors
2
High Bias corresponds to LNA_Mixer Setting of 33 in SPI Register 0x01
3
Low Bias corresponds to LNA_Mixer Setting of 12 in SPI Register 0x01
相關PDF資料 |
PDF描述 |
|---|---|
| AD9875BSTRL | Broadband Modem Mixed-Signal Front End |
| AD9875 | Broadband Modem Mixed-Signal Front End |
| AD9875-EB | Broadband Modem Mixed-Signal Front End |
| AD9875BST | Broadband Modem Mixed-Signal Front End |
| AD9876 | Broadband Modem Mixed-Signal Front End |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9874-EB | 制造商:Analog Devices 功能描述: |
| AD9874-EBZ | 功能描述:BOARD EVAL FOR AD9874 制造商:analog devices inc. 系列:- 零件狀態:有效 類型:數字轉換器 頻率:10MHz ~ 300MHz 配套使用產品/相關產品:AD9874 所含物品:板 標準包裝:1 |
| AD9875 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Broadband Modem Mixed-Signal Front End |
| AD9875BST | 制造商:Analog Devices 功能描述:Modem Chip Single 48-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:10B BROADBAND MODEM MXFE CONVERTER - Tape and Reel |
| AD9875BSTRL | 制造商:Analog Devices 功能描述:Modem Chip Single 48-Pin LQFP T/R |
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