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參數(shù)資料
| 型號(hào)： | AD9874EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | IF Digitizing Subsystem |
| 中文描述： | 中頻數(shù)字化子系統(tǒng) |
| 文件頁數(shù)： | 35/40頁 |
| 文件大小： | 744K |
| 代理商： | AD9874EB |
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REV. 0
AD9874
–35–
VCO
25
23
24
PE
PD
PC
33
SYNCB
31
FS
29
28
DOUTA
CLKOUT
35
f
REF
19
20
CLKP
CLKN
LOP
LON
43
42
IFIN
47
15
AD9874
MASTER
IOUTC
LOOP
FILTER
38
15
IOUTC
25
23
24
PE
PD
PC
35
LOP
LON
43
42
IFIN
47
31
FS
29
28
DOUTA
CLKOUT
33
SYNCB
TO
DSP
CLKP
CLKN
IOUTL
TO DSP
FROM
DSP
LOOP
FILTER
C
VAR
R
D
R
F
C
P
C
Z
0.1 F
L
OSC
R
BIAS
C
OSC
TO OTHER
AD9874s
FROM
CRYSTAL
OSCILLATION
VDDC
TO OTHER
AD9874s
AD9874
SLAVE
19
20
f
REF
Figure 28. Example of Synchronizing Multiple AD9874s
a higher
f
CLK
is typically more desirable given a choice, since the
first IF’s filtering requirements often depend on the transition
region between the IF frequency and the image band (i.e.,
±
f
CLK
/4 ).
Lastly, the output SSI clock rate,
f
CLKOUT
, and digital driver
strength should be set to their lowest possible settings to mini-
mize the potential harmful effects of digital induced noise while
preserving a reliable data link to the DSP. Note, the SSICRA,
SSICRB, and SSIORD Registers (i.e., 0x18, 0x19, and 0x1A)
provide a large degree of flexibility for optimization of the SSI
interface.
Synchronization of Multiple AD9874s
Some applications such as receiver diversity and beam steering
may require two or more AD9874s operating in parallel while
maintaining synchronization. Figure 28 shows an example of how
multiple AD9874s can be cascaded, with one device serving as
the master and the other devices serving as the slaves. In this
example, all of the devices have the exact same SPI register con-
figuration since they share the same SPI interface to the DSP.
Since the state of each of the AD9874’s internal counters is
unknown upon initialization, synchronization of the devices is
required via a SYNCB pulse (see Figure 4) to synchronize their
digital filters and ensure precise time alignment of the data streams.
Although all of the devices’ synthesizers are enabled, the LO and
CLK signals for the slaves(s) are derived from the masters’ synthe-
sizers and are referenced to an external crystal oscillator. All of
the necessary external components (i.e., loop filters, varactor, LC,
and VCO) to ensure proper closed-loop operation of these
synthesizers are included.
Note, while the VCO output of the LO synthesizer is ac-coupled
to the slave’s LO input(s), all of the CLK inputs of the devices
must be dc-coupled if the AD9874’s CLK oscillators are enabled.
This is due to the dc current required by the CLK oscillators in
each device. In essence, these negative impedance cores are oper-
ating in parallel, increasing the effective Q of the LC resonator
circuit. Note, RBIAS should be sized such that the sum of the
oscillators’ dc bias currents maintains a common-mode voltage
of around 1.6 V.
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PDF描述 |
|---|---|
| AD9875BSTRL | Broadband Modem Mixed-Signal Front End |
| AD9875 | Broadband Modem Mixed-Signal Front End |
| AD9875-EB | Broadband Modem Mixed-Signal Front End |
| AD9875BST | Broadband Modem Mixed-Signal Front End |
| AD9876 | Broadband Modem Mixed-Signal Front End |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9874-EB | 制造商:Analog Devices 功能描述: |
| AD9874-EBZ | 功能描述:BOARD EVAL FOR AD9874 制造商:analog devices inc. 系列:- 零件狀態(tài):有效 類型:數(shù)字轉(zhuǎn)換器 頻率:10MHz ~ 300MHz 配套使用產(chǎn)品/相關(guān)產(chǎn)品:AD9874 所含物品:板 標(biāo)準(zhǔn)包裝:1 |
| AD9875 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Broadband Modem Mixed-Signal Front End |
| AD9875BST | 制造商:Analog Devices 功能描述:Modem Chip Single 48-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:10B BROADBAND MODEM MXFE CONVERTER - Tape and Reel |
| AD9875BSTRL | 制造商:Analog Devices 功能描述:Modem Chip Single 48-Pin LQFP T/R |
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