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參數資料
| 型號： | AD9886KS-100 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | Analog Interface for Flat Panel Displays |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP160 |
| 封裝： | PLASTIC, MQFP-160 |
| 文件頁數： | 19/32頁 |
| 文件大?。?/td> | 248K |
| 代理商： | AD9886KS-100 |
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REV. 0
AD9886
–19–
2-Wire Serial Register Map
The AD9886 is initialized and controlled by a set of registers, which determine the operating modes. An external controller is
employed to write and read the Control Registers through the 2-line serial interface port.
Table V. Control Register Map
Write and
Read or
Read Only
Hex
Address
Default
Value
Register
Name
Bits
Function
0
0H
RO
7:0
Chip Revision
Bits 7 through 4 represent functional revisions to the analog interface.
Bits 3 through 0 represent nonfunctional related revisions.
Revision 0 = 0000 0000
01H
R/
W
7:0
01101001
PLL Div MSB
This register is for Bits [11:4] of the PLL divider. Larger values mean
the PLL operates at a faster rate. This register should be loaded first
whenever a change is needed. (This will give the PLL more time to
lock.) See Note 1.
02H
R/
W
7:4
1101
****
PLL Div LSB
Bits [7:4] LSBs of the PLL divider word. See Note 1.
03H
R/
W
7:2
1
*******
*
01
*****
VCO/CPMP
Bit 7—Must be set to 1 for proper device operation.
Bits [6:5] VCO Range. Selects VCO frequency range. (See PLL
description.)
Bits [4:2] Charge Pump Current. Varies the current that drives the
low-pass filter. (See PLL description.)
***
001
**
04H
R/
W
7:3
01000
***
Phase Adjust
ADC Clock phase adjustment. Larger values mean more delay.
(1 LSB = T/32.)
05H
R/
W
7:0
10000000
Clamp
Placement
Places the Clamp signal an integer number of clock periods after the trail-
ing edge of the Hsync signal.
06H
R/
W
7:0
10000000
Clamp
Duration
Number of clock periods that the Clamp signal is actively clamping.
07H
R/
W
7:0
00100000
Hsync Output
Pulsewidth
Sets the number of pixel clocks that HSOUT will remain active.
08H
R/
W
7:0
10000000
Red Gain
Controls ADC input range (Contrast) of each respective channel.
Bigger values give less contrast.
09H
R/
W
7:0
10000000
Green Gain
0AH
R/
W
7:0
10000000
Blue Gain
0BH
R/
W
7:1
1000000
*
Red Offset
Controls dc offset (Brightness) of each respective channel. Bigger
values decrease brightness.
0CH
R/
W
7:1
1000000
*
Green Offset
0DH
R/
W
7:1
1000000
*
Blue Offset
0EH
R/
W
7:3
1
*******
Mode
Control 1
Bit 7—Channel Mode. Determines Single Channel or Dual Channel
Output Mode. (Logic 0 = Single Channel Mode, Logic 1 = Dual
Channel Mode.)
Bit 6—Output Mode. Determine Interleaved or Parallel Output Mode.
(Logic 0 = Interleaved Mode, Logic 1 = Parallel Mode.)
Bit 5—A/B Invert. Determines which port outputs the first data byte
after Hsync. (Logic 0 = A Port, Logic 1 = B Port.)
Bit 4—Hsync Output polarity. (Logic 0 = Logic High Sync, Logic 1 =
Logic Low Sync.)
Bit 3—Vsync Output Invert. (Logic 0 = No Invert, Logic 1 = Invert.)
*
1
******
**
0
*****
***
1
****
****
1
***
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相關代理商/技術參數 |
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|---|---|
| AD9886KS-140 | 制造商:Rochester Electronics LLC 功能描述:A/D INTERFACE FOR FLAT PANEL, 140 MSPS - Bulk 制造商:Analog Devices 功能描述: |
| AD9887 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Interface for Flat Panel Displays |
| AD9887/PCB | 制造商:Analog Devices 功能描述:INTRFC DUAL FOR FLAT PNL DISPLAYS 160MQFP - Bulk |
| AD9887A | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Interface for Flat Panel Displays |
| AD9887A/PCB | 制造商:Analog Devices 功能描述:INTRFC FOR FLAT PNL DISPLAY 16SOIC W - Bulk |
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