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參數(shù)資料
| 型號： | AD9886KS-100 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | Analog Interface for Flat Panel Displays |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP160 |
| 封裝： | PLASTIC, MQFP-160 |
| 文件頁數(shù)： | 30/32頁 |
| 文件大小： | 248K |
| 代理商： | AD9886KS-100 |
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REV. 0
AD9886
–30–
Table XLV. Control of the Sync Block Muxes via the
Serial Register
Control
Bit
State
Mux
Nos.
Serial Bus
Control Bit
Result
1 and 2
12H: Bit 4
0
1
0
1
Pass Hsync
Pass Sync-on-Green
Pass Vsync
Pass Sync Separator Signal
4
12H: Bit 2
Sync Slicer
The purpose of the sync slicer is to extract the sync signal from
the green graphics channel. A sync signal is not present on all
graphics systems, only those with “sync-on-green.” The sync
signal is extracted from the green channel in a two step process.
First, the SOG input is clamped to its negative peak (typically
0.3 V below the black level). Next, the signal goes to a compara-
tor with a trigger level that is 0.15 V above the clamped level.
The “sliced” sync is typically a composite sync signal containing
both Hsync and Vsync.
Sync Separator
A sync separator extracts the Vsync signal from a composite
sync signal. It does this through a low-pass filter-like or integrator-
like operation. It works on the idea that the Vsync signal stays
active for a much longer time than the Hsync signal, so it rejects
any signal shorter than a threshold value, which is somewhere
between an Hsync pulsewidth and a Vsync pulsewidth.
The sync separator on the AD9886 is simply an 8-bit digital
counter with a 5 MHz clock. It works independently of the
polarity of the composite sync signal. (Polarities are determined
elsewhere on the chip.) The basic idea is that the counter counts
up when Hsync pulses are present. But since Hsync pulses are
relatively short in width, the counter only reaches a value of N
before the pulse ends. It then starts counting down eventually
reaching 0 before the next Hsync pulse arrives. The specific
value of N will vary for different video modes, but will always be
less than 255. For example with a 1
μ
s width Hsync, the counter
will only reach 5 (1
μ
s/200 ns = 5). Now, when Vsync is present
on the composite sync the counter will also count up. However,
since the Vsync signal is much longer, it will count to a higher
number M. For most video modes, M will be at least 255. So,
Vsync can be detected on the composite sync signal by detecting
when the counter counts to higher than N. The specific count
that triggers detection (T) can be programmed through the
serial register (0fh).
Once Vsync has been detected, there is a similar process to detect
when it goes inactive. At detection, the counter first resets to 0,
then starts counting up when Vsync goes away. Similar to the
previous case, it will detect the absence of Vsync when the
counter reaches the threshold count (T). In this way, it will
reject noise and/or serration pulses. Once Vsync is detected to
be absent, the counter resets to 0 and begins the cycle again.
SYNC STRIPPER
ACTIVITY
DETECT
NEGATIVE PEAK
CLAMP
COMP
SYNC
SOG
HSYNC IN
ACTIVITY
DETECT
POLARITY
DETECT
CLOCK
GENERATOR
COAST
MUX 2
HSYNC OUT
PIXEL CLOCK
POLARITY
DETECT
MUX 1
SYNC SEPARATOR
INTEGRATOR
VSYNC
HSYNC OUT
VSYNC OUT
DE
MUX 4
VSYNC IN
1/S
PLL
HSYNC
ACTIVITY
DETECT
AD9886
SOG OUT
Figure 29. Sync Processing Block Diagram
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| AD9886KS-140 | Analog Interface for Flat Panel Displays |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9886KS-140 | 制造商:Rochester Electronics LLC 功能描述:A/D INTERFACE FOR FLAT PANEL, 140 MSPS - Bulk 制造商:Analog Devices 功能描述: |
| AD9887 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Interface for Flat Panel Displays |
| AD9887/PCB | 制造商:Analog Devices 功能描述:INTRFC DUAL FOR FLAT PNL DISPLAYS 160MQFP - Bulk |
| AD9887A | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Interface for Flat Panel Displays |
| AD9887A/PCB | 制造商:Analog Devices 功能描述:INTRFC FOR FLAT PNL DISPLAY 16SOIC W - Bulk |
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