- 您現在的位置：買賣IC網 > PDF目錄373970 > AD9886KS-100 (ANALOG DEVICES INC) Analog Interface for Flat Panel Displays PDF資料下載
參數資料
| 型號： | AD9886KS-100 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | Analog Interface for Flat Panel Displays |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP160 |
| 封裝： | PLASTIC, MQFP-160 |
| 文件頁數： | 22/32頁 |
| 文件大小： | 248K |
| 代理商： | AD9886KS-100 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁當前第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁
REV. 0
AD9886
–22–
TWO-WIRE SERIAL CONTROL REGISTER DETAIL
CHIP IDENTIFICATION
00
7–0
Chip Revision
Bits 7 through 4 represent functional revisions to the
analog interface. Changes in these bits will generally
indicate that software and/or hardware changes will be
required for the chip to work properly. Bits 3 through 0
represent nonfunctional related revisions and are reset to
0000 whenever the MSBs are changed. Changes in these
bits are considered transparent to the user.
PLL DIVIDER CONTROL
01
7–0
PLL Divide Ratio MSBs
The eight most significant bits of the 12-bit PLL divide ratio
PLLDIV. (The operational divide ratio is PLLDIV + 1.)
The PLL derives a master clock from an incoming Hsync
signal. The master clock frequency is then divided by an
integer value, such that the output is phase-locked to
Hsync. This PLLDIV value determines the number of
pixel times (pixels plus horizontal blanking overhead) per
line. This is typically 20% to 30% more than the number
of active pixels in the display.
The 12-bit value of the PLL divider supports divide ratios
from 2 to 4095. The higher the value loaded in this regis-
ter, the higher the resulting clock frequency with respect
to a fixed Hsync frequency.
VESA has established some standard timing specifications,
which will assist in determining the value for PLLDIV as
a function of horizontal and vertical display resolution
and frame rate (Table IV).
However, many computer systems do not conform pre-
cisely to the recommendations, and these numbers should
be used only as a guide. The display system manufacturer
should provide automatic or manual means for optimizing
PLLDIV. An incorrectly set PLLDIV will usually produce
one or more vertical noise bars on the display. The greater
the error, the greater the number of bars produced.
The power-up default value of PLLDIV is 1693
(PLLDIVM = 69h, PLLDIVL = Dxh).
The AD9886 updates the full divide ratio only when the
LSBs are changed. Writing to this register by itself will not
trigger an update.
02
7–4
PLL Divide Ratio LSBs
The four least significant bits of the 12-bit PLL divide ratio
PLLDIV. The operational divide ratio is PLLDIV + 1.
The power-up default value of PLLDIV is 1693
(PLLDIVM = 69h, PLLDIVL = Dxh).
The AD9886 updates the full divide ratio only when this
register is written to.
CLOCK GENERATOR CONTROL
03
7 TEST
Set to One
03
6–5
Two bits that establish the operating range of the clock
generator.
VCORNGE must be set to correspond with the desired
operating frequency (incoming pixel rate).
VCO Range Select
The PLL gives the best jitter performance at high fre-
quencies. For this reason, in order to output low pixel
rates and still get good jitter performance, the PLL actu-
ally operates at a higher frequency but then divides down
the clock rate afterwards. Table VI shows the pixel rates
for each VCO range setting. The PLL output divisor is
automatically selected with the VCO range setting.
Table VI. VCO Ranges
VCORNGE
Pixel Rate Range
00
01
10
11
12–35
35–70
70–110
110–140
The power-up default value is = 01.
4–2
CURRENT Charge Pump Current
Three bits that establish the current driving the loop filter
in the clock generator.
03
Table VII. Charge Pump Currents
CURRENT
Current ( A)
000
001
010
011
100
101
110
111
50
100
150
250
350
500
750
1500
CURRENT must be set to correspond with the desired
operating frequency (incoming pixel rate).
The power-up default value is CURRENT = 001.
7–3
Clock Phase Adjust
A five-bit value that adjusts the sampling phase in 32 steps
across one pixel time. Each step represents an 11.25
°
shift
in sampling phase.
The power-up default value is 16.
04
CLAMP TIMING
05
7–0
An eight-bit register that sets the position of the internally
generated clamp.
When EXTCLMP = 0, a clamp signal is generated inter-
nally, at a position established by the clamp placement and
for a duration set by the clamp duration. Clamping is
started (Clamp Placement) pixel periods after the trailing
edge of Hsync. The clamp placement may be programmed
to any value between 1 and 255. A value of 0 is not
supported.
The clamp should be placed during a time that the input
signal presents a stable black-level reference, usually the
back porch period between Hsync and the image.
When EXTCLMP = 1, this register is ignored.
Clamp Placement
相關PDF資料 |
PDF描述 |
|---|---|
| AD9886KS-140 | Analog Interface for Flat Panel Displays |
| AD9898 | CCD Signal Processor with Precision Timing⑩ Generator |
| AD9898KCP-20 | CCD Signal Processor with Precision Timing⑩ Generator |
| AD9898KCPRL-20 | TVPS00RF-21-41S W/ PC CON |
| AD9901 | Ultrahigh Speed Phase/Frequency Discriminator |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9886KS-140 | 制造商:Rochester Electronics LLC 功能描述:A/D INTERFACE FOR FLAT PANEL, 140 MSPS - Bulk 制造商:Analog Devices 功能描述: |
| AD9887 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Interface for Flat Panel Displays |
| AD9887/PCB | 制造商:Analog Devices 功能描述:INTRFC DUAL FOR FLAT PNL DISPLAYS 160MQFP - Bulk |
| AD9887A | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Interface for Flat Panel Displays |
| AD9887A/PCB | 制造商:Analog Devices 功能描述:INTRFC FOR FLAT PNL DISPLAY 16SOIC W - Bulk |
發布緊急采購，3分鐘左右您將得到回復。