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參數資料
| 型號： | AD9886KS-100 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | Analog Interface for Flat Panel Displays |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP160 |
| 封裝： | PLASTIC, MQFP-160 |
| 文件頁數： | 24/32頁 |
| 文件大小： | 248K |
| 代理商： | AD9886KS-100 |
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REV. 0
AD9886
–24–
0E
4
One bit that determines the polarity of the HSYNC out-
put and the SOG output. Table XI shows the effect of this
option. SYNC indicates the logic state of the sync pulse.
HSYNC Output Polarity
Table XI. HSYNC Output Polarity Settings
Setting
SYNC
0
1
Logic 1 (Positive Polarity)
Logic 0 (Negative Polarity)
The default setting for this register is 1. (This option
works on both the analog and digital interfaces.)
3
VSYNC Output Invert
One bit that inverts the polarity of the VSYNC output.
Table XII shows the effect of this option.
0E
Table XII. VSYNC Output Polarity Settings
Setting
VSYNC Output
0
1
No Invert
Invert
The default setting for this register is 1. (This option
works on both the analog and digital interfaces.)
0F
7
A bit that must be set to indicate the polarity of the HSYNC
signal that is applied to the PLL HSYNC input.
HSPOL HSYNC Input Polarity
Table XIII. HSYNC Input Polarity Settings
HSPOL
Function
0
1
Active LOW
Active HIGH
Active LOW is the traditional negative-going Hsync pulse.
All timing is based on the leading edge of Hsync, which is
the FALLING edge. The rising edge has no effect.
Active HIGH is inverted from the traditional Hsync, with
a positive-going pulse. This means that timing will be
based on the leading edge of Hsync, which is now the
RISING edge.
The device will operate if this bit is set incorrectly, but the
internally generated clamp position, as established by
CLPOS, will not be placed as expected, which may gener-
ate clamping errors.
The power-up default value is HSPOL = 1.
6 COAST Input Polarity
A bit to indicate the polarity of the COAST signal that is
applied to the PLL COAST input.
0F
Table XIV. COAST Input Polarity Settings
CSTPOL
Function
0
1
Active LOW
Active HIGH
Active LOW means that the clock generator will ignore
Hsync inputs when COAST is LOW, and continue oper-
ating at the same nominal frequency until COAST goes
HIGH.
Active HIGH means that the clock generator will ignore
Hsync inputs when COAST is HIGH, and continue oper-
ating at the same nominal frequency until COAST goes
LOW.
This function needs to be used along with the COAST
polarity override bit (Register 14, Bit 1).
The power-up default value is CSTPOL = 1.
5 Clamp Input Signal Source
A bit that determines the source of clamp timing.
0F
Table XV. Clamp Input Signal Source Settings
EXTCLMP
Function
0
1
Internally-Generated Clamp
Externally-Provided Clamp Signal
A 0 enables the clamp timing circuitry controlled by
CLPLACE and CLDUR. The clamp position and dura-
tion is counted from the leading edge of Hsync.
A 1 enables the external CLAMP input pin. The three
channels are clamped when the CLAMP signal is
active. The polarity of CLAMP is determined by the
CLAMPOL bit.
The power-up default value is EXTCLMP = 0.
4
CLAMP Input Signal Polarity
A bit that determines the polarity of the externally pro-
vided CLAMP signal.
0F
Table XVI. CLAMP Input Signal Polarity Settings
EXTCLMP
Function
0
1
Active LOW
Active HIGH
A Logic 0 means that the circuit will clamp when CLAMP
is HIGH, and it will pass the signal to the ADC when
CLAMP is LOW.
A Logic 1 means that the circuit will clamp when CLAMP
is LOW, and it will pass the signal to the ADC when
CLAMP is HIGH.
The power-up default value is CLAMPOL = 1.
3 External Clock Select
A bit that determines the source of the pixel clock.
0F
Table XVII. External Clock Select Settings
EXTCLK
Function
0
1
Internally Generated Clock
Externally Provided Clock Signal
A Logic 0 enables the internal PLL that generates the
pixel clock from an externally provided Hsync.
A Logic 1 enables the external CKEXT input pin. In this
mode, the PLL Divide Ratio (PLLDIV) is ignored. The
clock phase adjust (PHASE) is still functional.
The power-up default value is EXTCLK = 0.
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