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參數資料
| 型號： | AD9886KS-100 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | Analog Interface for Flat Panel Displays |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP160 |
| 封裝： | PLASTIC, MQFP-160 |
| 文件頁數： | 25/32頁 |
| 文件大小： | 248K |
| 代理商： | AD9886KS-100 |
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REV. 0
AD9886
–25–
0F
2
A bit that determines whether the red channel is clamped
to ground or to midscale. For RGB video, all three chan-
nels are referenced to ground. For YcbCr (or YUV), the
Y channel is referenced to ground, but the CbCr channels
are referenced to midscale. Clamping to midscale actually
clamps to Pin 118, R
CLAMP
V.
Red Clamp Select
Table XVIII. Red Clamp Select Settings
Clamp
Function
0
1
Clamp to Ground
Clamp to Midscale (Pin 118)
The default setting for this register is 0.
1
Green Clamp Select
A bit that determines whether the green channel is clamped
to ground or to midscale.
0F
Table XIX. Green Clamp Select Settings
Clamp
Function
0
1
Clamp to Ground
Clamp to Midscale (Pin 109)
The default setting for this register is 0.
0
Blue Clamp Select
A bit that determines whether the blue channel is clamped
to ground or to midscale.
0F
Table XX. Blue Clamp Select Settings
Clamp
Function
0
1
Clamp to Ground
Clamp to Midscale (Pin 99)
The default setting for this register is 0.
MODE CONTROL 2
10
7
Clk Inv Data Output Clock Invert
A control bit for the inversion of the output data clocks,
(Pins 134, 135). This function works only for the digital
interface. When not inverted, data is output on the rising
edge of the data clock. See timing diagrams to see how
this affects timing.
Table XXI. Clock Output Invert Settings
Clk Inv
Function
0
1
Not Inverted
Inverted
The default for this register is 0, not inverted.
10
6
Pix Select
This bit selects either 1 or 2 pixels per clock mode for the
digital interface. It determines whether the data comes out
of a single port (even port only), at the full data rate or
out of two ports (both even and odd ports) at one-half the
full data rate per port. A Logic 0 selects 1 pixel per clock
(even port only). A Logic 1 selects 2 pixels per clock (both
ports). See the Digital Interface Timing Diagrams, Fig-
ures 29 to 32, for a visual representation of this function.
Note: This function operates exactly like the DEMUX
function on the analog interface.
Table XXII. Pix Select Settings
Pix Select
Function
0
1
1 Pixel per Clock
2 Pixels per Clock
The default for this register is 0, 1 pixel per clock.
5, 4
Output Drive
These two bits select the drive strength for the high-speed
digital outputs (all data output and clock output pins).
Higher drive strength results in faster rise/fall times and in
general makes it easier to capture data. Lower drive strength
results in slower rise/fall times and helps to reduce EMI
and digitally generated power supply noise. The exact
timing specifications for each of these modes are specified
in the Table IV.
10
Table XXIII. Output Drive Strength Settings
Bit 5
Bit 4
Result
1
1
0
1
0
X
High Drive Strength
Medium Drive Strength
Low Drive Strength
The default for this register is 11, high drive strength. (This
option works on both the analog and digital interfaces.)
3 P
DO
—Power-Down Outputs
A bit that can put the outputs in a high impedance mode.
This applies only to the 48 data output pins and the two
data clock outputs pins.
10
Table XXIV. Power-Down Outputs Settings
CKINV
Function
0
1
Normal Operation
Three-State
The default for this register is 0. (This option works on
both the analog and digital interfaces.)
2
Sync Detect Polarity
This pin controls the polarity of the Sync Detect output
pin (Pin 136).
10
Table XXV. Sync Detect Polarity Settings
Polarity
Function
0
1
Activity = Logic 1 Output
Activity = Logic 0 Output
The default for this register is 0. (This option works on
both the analog and digital interfaces.)
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| AD9886KS-140 | 制造商:Rochester Electronics LLC 功能描述:A/D INTERFACE FOR FLAT PANEL, 140 MSPS - Bulk 制造商:Analog Devices 功能描述: |
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