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參數資料
| 型號： | AD9927BBCZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | 14-Bit CCD Signal Processor with V-Driver and Precision TimingTM Generator |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, BGA128 |
| 封裝： | 9 X 9 MM, LEAD FREE, MO-225, CSP_BGA-128 |
| 文件頁數： | 31/100頁 |
| 文件大小： | 784K |
| 代理商： | AD9927BBCZ |
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AD9927
VERTICAL SEQUENCES (VSEQ)
The vertical sequences are created by selecting one of the
V-pattern groups and adding repeats, start position, horizontal
clamping, and blanking information. The V-sequences are
programmed using the registers shown in Table 14. Figure 36
shows how the different registers are used to generate each
V-sequence.
Rev. 0 | Page 31 of 100
The VPATSELA, VPATSELB, VPATSELC, and VPATSELD
registers select which V-pattern is used in a given V-sequence.
Having four groups available allows different vertical outputs to
be mapped to different V-patterns. The selected V-pattern group
can have repetitions added for high speed line shifts or for line
binning by using the VREP registers for odd and even lines.
Generally, the same number of repetitions is programmed
into both registers. If a different number of repetitions is
required on odd and even lines, separate values can be used for
each register (see the Generating Line Alternation for V-
Sequences and HBLK section). The VSTARTA and VSTARTB
registers specify where in the line the V-pattern group starts.
The VMASK_EN register is used in conjunction with the
FREEZE/RESUME registers to enable optional masking of the
V-outputs. Either or both of the FREEZE1/RESUME1 and
FREEZE2/RESUME2 registers can be enabled.
The line length (in pixels) is programmable using the HDLEN
registers. Each V-sequence can have a different line length to
accommodate various image readout techniques. The maximum
number of pixels per line is 8192. The last line of the field is
programmed separately using the HDLASTLEN register, which
is located in the field register section.
VREP 3
HD
XV1 TO XV24
V-PATTERN GROUP
1
3
CLPOB
HBLK
2
4
4
VREP 2
5
6
PROGRAMMABLE SETTINGS FOR EACH VERTICAL SEQUENCE:
1
START POSITION IN THE LINE OF SELECTED V-PATTERN GROUP.
2
HD LINE LENGTH.
3
V-PATTERN SELECT (VPATSEL) TO SELECT ANY V-PATTERN GROUP.
4
NUMBER OF REPETITIONS OF THE V-PATTERN GROUP (IF NEEDED).
5
START POLARITY AND TOGGLE POSITIONS FOR CLPOB AND PBLK SIGNALS.
6
MASKING POLARITY AND TOGGLE POSITIONS FOR HBLK SIGNAL.
0
Figure 36. V-Sequence Programmability
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相關代理商/技術參數 |
參數描述 |
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| AD9927BBCZRL | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD9928 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Channel 14-Bit CCD Signal Processor with V-Driver and Precision Timing Generator |
| AD9928BBCZ | 功能描述:IC CCD SIGNAL PROCESSR 128CSPBGA RoHS:是 類別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 產品變化通告:Product Discontinuation 07/Mar/2011 標準包裝:3,000 系列:OMNITUNE™ 類型:調諧器 應用:移動電話，手機，視頻顯示器 安裝類型:表面貼裝 封裝/外殼:65-WFBGA 供應商設備封裝:PG-WFSGA-65 包裝:帶卷 (TR) 其它名稱:SP000365064 |
| AD9928BBCZ-60 | 制造商:Analog Devices 功能描述:- Trays |
| AD9928BBCZRL | 功能描述:IC CCD SIGNAL PROCESSR 128CSPBGA RoHS:否 類別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 產品變化通告:Product Discontinuation 07/Mar/2011 標準包裝:3,000 系列:OMNITUNE™ 類型:調諧器 應用:移動電話，手機，視頻顯示器 安裝類型:表面貼裝 封裝/外殼:65-WFBGA 供應商設備封裝:PG-WFSGA-65 包裝:帶卷 (TR) 其它名稱:SP000365064 |
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