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參數資料
| 型號： | AD9927BBCZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | 14-Bit CCD Signal Processor with V-Driver and Precision TimingTM Generator |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, BGA128 |
| 封裝： | 9 X 9 MM, LEAD FREE, MO-225, CSP_BGA-128 |
| 文件頁數： | 32/100頁 |
| 文件大小： | 784K |
| 代理商： | AD9927BBCZ |
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AD9927
Table 14. Summary of V-Sequence Registers (see Table 10 and Table 11 for the HBLK, CLPOB, and PBLK Register Summary)
Register
Length Description
HOLD
4b
Use in conjunction with VMASK_EN.
1 = HOLD function instead of FREEZE/RESUME function.
VMASK_EN
4b
Enables the masking of V1 to V24 outputs at the locations specified by the FREEZE/RESUME registers.
1= enable masking for all groups. One bit for each set of Freeze and Resume Positions 1 to 4.
CONCAT_GRP
4b
Combines toggle positions of Groups A/B/C/D when enabled. Only Group A settings for start, polarity,
length, and repetition are used when this mode is selected.
0 = disable.
1 = enable the addition of all toggle positions from VPATSELA/B/C/D.
2 = test mode only. Do not use.
…
15 = test mode only. Do not use.
VREP_MODE
2b
Selects line alternation for V-output repetitions. Note separate control for Group A and Groups B/C/D.
0 = disable alternation. Group A uses VREPA_1, Groups B/C/D use VREP _EVEN for all lines.
1 = 2-line. Group A alternates VREPA_1 and VREPA_2. Groups B/C/D alternate VREP_EVEN and VREP_ODD.
2 = 3-line. Group A alternates VREPA_1, VREPA_2, and VREPA_3. Groups B/C/D follow a VREP_EVEN,
VREP_ODD, VREP_ODD, VREP_EVEN, VREP_ODD, VREP_ODD pattern.
3 = 4-line. Group A alternates VREPA_1, VREPA_2, VREPA_3, VREPA_4. Groups B/C/D follow 2-line alternation.
LASTREPLEN_EN
4b
Enables a separate pattern length to be used during the last repetition of the V-sequence. One bit for
each group (A, B, C, and D). Set bit high to enable. Group A is the LSB. Recommended value is enabled.
LASTTOG_EN
4b
Enables a final toggle position to be added at the end of the V-sequence. The toggle position is shared
by all V-outputs in the same group. One bit for each group. Set bit high to enable. Group A is the LSB.
HDLENE
13b
HD line length for even lines in the V-sequence.
HDLEN0
13b
HD line length for odd lines in the V-sequence.
VPOL_A
24b
Group A start polarity bits for each XV1 to XV24 signal.
VPOL_B
24b
Group B start polarity bits for each XV1 to XV24 signal.
VPOL_C
24b
Group C start polarity bits for each XV1 to XV24 signal.
VPOL_D
24b
Group D start polarity bits for each XV1 to XV24 signal.
GROUPSEL_0
24b
Assigns each XV1 to XV12 signal to either Group A/B/C/D. Two bits for each signal. Bits [1:0] are for XV1,
Bits [3:2] are for XV2 … Bits [23:22] are for XV12.
0 = assign to Group A, 1 = Group B, 2 = Group C, and 3 = Group D.
GROUPSEL_1
24b
Assigns each XV13 to XV24 signal to either Group A/B/C/D. Two bits for each signal. Bits [1:0] are for XV13,
Bits [3:2] are for XV14 … Bits [23:22] are for XV24.
0 = assign to Group A, 1 = Group B, 2 = Group C, and 3 = Group D.
VPATSELA
5b
Selected V-pattern for Group A.
VPATSELB
5b
Selected V-pattern for Group B.
VPATSELC
5b
Selected V-pattern for Group C.
VPATSELD
5b
Selected V-pattern for Group D.
VSTARTA
13b
Start position for the selected V-pattern Group A.
VSTARTB
13b
Start position for the selected V-pattern Group B.
VSTARTC
13b
Start position for the selected V-pattern Group C.
VSTARTD
13b
Start position for the selected V-pattern Group D.
VLENA
13b
Length of selected V-pattern Group A.
VLENB
13b
Length of selected V-pattern Group B.
VLENC
13b
Length of selected V-pattern Group C.
VLEND
13b
Length of selected V-pattern Group D.
VREPA_1
13b
Number of repetitions for the V-Pattern Group A for first lines (even).
VREPA_2
13b
Number of repetitions for the V-Pattern Group A for second lines (odd).
VREPA_3
13b
Number of repetitions for the V-Pattern Group A for third lines.
VREPA_4
13b
Number of repetitions for the V-Pattern Group A for fourth lines.
VREPB_ODD
13b
Number of repetitions for the V-Pattern Group B for odd lines.
VREPC_ODD
13b
Number of repetitions for the V-Pattern Group C for odd lines.
Rev. 0 | Page 32 of 100
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| AD9928 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Channel 14-Bit CCD Signal Processor with V-Driver and Precision Timing Generator |
| AD9928BBCZ | 功能描述:IC CCD SIGNAL PROCESSR 128CSPBGA RoHS:是 類別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 產品變化通告:Product Discontinuation 07/Mar/2011 標準包裝:3,000 系列:OMNITUNE™ 類型:調諧器 應用:移動電話，手機，視頻顯示器 安裝類型:表面貼裝 封裝/外殼:65-WFBGA 供應商設備封裝:PG-WFSGA-65 包裝:帶卷 (TR) 其它名稱:SP000365064 |
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