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參數資料
| 型號： | AD9927BBCZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | 14-Bit CCD Signal Processor with V-Driver and Precision TimingTM Generator |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, BGA128 |
| 封裝： | 9 X 9 MM, LEAD FREE, MO-225, CSP_BGA-128 |
| 文件頁數： | 98/100頁 |
| 文件大小： | 784K |
| 代理商： | AD9927BBCZ |
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AD9927
Table 61. Field Registers
Data
Bits
00
[4:0]
[9:5]
[14:10]
[19:15]
[24:20]
01
[4:0]
[9:5]
[14:10]
[19:15]
[21:20]
Rev. 0 | Page 98 of 100
Address
Default
Value
X
X
X
X
X
X
X
X
X
Update
Type
VD
VD
Name
SEQ0
SEQ1
SEQ2
SEQ3
SEQ4
SEQ5
SEQ6
SEQ7
SEQ8
MULT_SWEEP0
Description
Selected V-sequence for first region in the field.
Selected V-sequence for second region in the field.
Selected V-sequence for third region in the field.
Selected V-sequence for fourth region in the field.
Selected V-sequence for fifth region in the field.
Selected V-sequence for sixth region in the field.
Selected V-sequence for seventh region in the field.
Selected V-sequence for eighth region in the field.
Selected V-sequence for ninth region in the field.
Enables multiplier mode and/or sweep mode for Region 0.
0: multiplier off/sweep off; 1: multiplier off/sweep on;
2: multiplier on/sweep off; 3: multiplier on/sweep on.
Enables multiplier mode and/or sweep mode for Region 2.
Enables multiplier mode and/or sweep mode for Region 1.
HD last line length. Line length of last line in the field.
Enables multiplier mode and/or sweep mode for Region 3.
Enables multiplier mode and/or sweep mode for Region 4.
Enables multiplier mode and/or sweep mode for Region 5.
Enables multiplier mode and/or sweep mode for Region 6.
Enables multiplier mode and/or sweep mode for Region 7.
Enables multiplier mode and/or sweep mode for Region 8.
HD last line length Bit [13] when 14-bit H-counter is enabled.
V-Sequence Change Position 0.
V-Sequence Change Position 1.
V-Sequence Change Position 2.
V-Sequence Change Position 3.
V-Sequence Change Position 4.
V-Sequence Change Position 5.
V-Sequence Change Position 6.
V-Sequence Change Position 7.
V-Sequence Change Position 8.
VD field length (number of lines in the field).
SG Active Line 1.
SG Active Line 2 (set to SG Active Line 1 or maximum if not
used).
Masking of VSG outputs during SG active line.
CLPOB Mask Region 1 start position. Set to 8191 to disable.
CLPOB Mask Region 1 end position. Set to 0 to disable.
CLPOB Mask Region 2 start position. Set to 8191 to disable.
CLPOB Mask Region 2 end position. Set to 0 to disable.
CLPOB Mask Region 3 start position. Set to 8191 to disable.
CLPOB Mask Region 3 end position. Set to 0 to disable.
PBLK Mask Region 1 start position. Set to 8191 to disable.
PBLK Mask Region 1 end position. Set to 0 to disable.
PBLK Mask Region 2 start position. Set to 8191 to disable.
PBLK Mask Region 2 end position. Set to 0 to disable.
PBLK Mask Region 3 start position. Set to 8191 to disable.
PBLK Mask Region 3 end position. Set to 0 to disable.
02
03
04
05
06
07
08
[23:22]
[25:24]
[12:0]
[14:13]
[16:15]
[18:17]
[20:19]
[22:21]
[24:23]
[25]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
VD
VD
VD
VD
VD
VD
VD
MULT_SWEEP1
MULT_SWEEP2
HDLASTLEN
MULT_SWEEP3
MULT_SWEEP4
MULT_SWEEP5
MULT_SWEEP6
MULT_SWEEP7
MULT_SWEEP8
HDLASTLEN_13
SCP0
SCP1
SCP2
SCP3
SCP4
SCP5
SCP6
SCP7
SCP8
VDLEN
SGACTLINE1
SGACTLINE2
09
0A
0B
0C
0D
0E
0F
[23:0]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
X
X
X
X
X
X
X
X
X
X
X
X
X
VD
VD
VD
VD
VD
VD
VD
SGMASK
CLPMASKSTART1
CLPMASKEND1
CLPMASKSTART2
CLPMASKEND2
CLPMASKSTART3
CLPMASKEND3
PBLKMASKSTART1
PBLKMASKEND1
PBLKMASKSTART2
PBLKMASKEND2
PBLKMASKSTART3
PBLKMASKEND3
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| AD9928BBCZ | 功能描述:IC CCD SIGNAL PROCESSR 128CSPBGA RoHS:是 類別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 產品變化通告:Product Discontinuation 07/Mar/2011 標準包裝:3,000 系列:OMNITUNE™ 類型:調諧器 應用:移動電話，手機，視頻顯示器 安裝類型:表面貼裝 封裝/外殼:65-WFBGA 供應商設備封裝:PG-WFSGA-65 包裝:帶卷 (TR) 其它名稱:SP000365064 |
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