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參數(shù)資料
型號(hào)： AD9927BBCZ
廠商： ANALOG DEVICES INC
元件分類： 消費(fèi)家電
英文描述： 14-Bit CCD Signal Processor with V-Driver and Precision TimingTM Generator
中文描述： SPECIALTY CONSUMER CIRCUIT, BGA128
封裝： 9 X 9 MM, LEAD FREE, MO-225, CSP_BGA-128
文件頁(yè)數(shù)： 33/100頁(yè)
文件大小： 784K
代理商： AD9927BBCZ
AD9927
Register
VREPD_ODD
VREPB_EVEN
VREPC_EVEN
VREPD_EVEN
FREEZE1
Rev. 0 | Page 33 of 100
Length Description
13b
Number of repetitions for the V-Pattern Group D for odd lines.
13b
Number of repetitions for the V-Pattern Group B for even lines.
13b
Number of repetitions for the V-Pattern Group C for even lines.
13b
Number of repetitions for the V-Pattern Group D for even lines.
13b
Pixel location where the V-outputs freeze or hold (see VMASK_EN). Also used as VALTSEL0_EVEN [12:0]
register when Special VSEQALT_EN mode is enabled.
13b
Pixel location where the V-outputs freeze or hold (see VMASK_EN). Also used as VALTSEL1_EVEN [12:0]
register when Special VSEQALT_EN mode is enabled.
13b
Pixel location where the V-outputs freeze or hold (see VMASK_EN). Also used as VALTSEL0_ODD [12:0]
register when Special VSEQALT_EN mode is enabled.
13b
Pixel location where the V-outputs freeze or hold (see VMASK_EN). Also used as VALTSEL1_ODD [12:0]
register when Special VSEQALT_EN mode is enabled.
13b
Pixel location where the V-outputs resume operation (see VMASK_EN). Also used as VALTSEL0_EVEN [17:13]
register when Special VSEQALT_EN mode is enabled.
13b
Pixel location where the V-outputs resume operation (see VMASK_EN). Also used as VALTSEL1_EVEN [17:13]
register when Special VSEQALT_EN mode is enabled.
13b
Pixel location where the V-outputs resume operation (see VMASK_EN). Also used as VALTSEL0_ODD [17:13]
register when Special VSEQALT_EN mode is enabled.
13b
Pixel location where the V-outputs resume operation (see VMASK_EN). Also used as VALTSEL1_ODD [17:13]
register when Special VSEQALT_EN mode is enabled.
13b
Separate length for last repetition of vertical pulses. Must be enabled using LASTREPLEN_EN.
Should be programmed to a value equal to the VLENA register.
13b
Separate length for last repetition of vertical pulses. Must be enabled using LASTREPLEN_EN.
Should be programmed to a value equal to the VLENB register.
13b
Separate length for last repetition of vertical pulses. Must be enabled using LASTREPLEN_EN.
Should be programmed to a value equal to the VLENC register.
13b
Separate length for last repetition of vertical pulses. Must be enabled using LASTREPLEN_EN.
Should be programmed to a value equal to the VLEND register.
13b
Optional fifth toggle position for the vertical signals. Must be enabled using LASTTOG_EN.
Note that the toggle position is common for all vertical signals.
13b
Optional fifth toggle position for the vertical signals. Must be enabled using LASTTOG_EN.
Note that the toggle position is common for all vertical signals.
13b
Optional fifth toggle position for the vertical signals. Must be enabled using LASTTOG_EN.
Note that the toggle position is common for all vertical signals.
13b
Optional fifth toggle position for the vertical signals. Must be enabled using LASTTOG_EN.
Note that the toggle position is common for all vertical signals.
1b
Special V-sequence alternation mode is enabled when this register is programmed high.
1b
Enables the use of FREEZE/RESUME register locations to specify the VALTSEL0 and VALTSEL1 registers.
Must be enabled if VSEQALT mode is enabled.
18b
Select lines for special V-sequence alternation mode for even lines. Used to concatenate VPAT Groups A/B/C/D
into unique merged patterns. Setting is used to specify one segment, with up to a maximum of 18 segments.
18b
Select lines for special V-sequence alternation mode for even lines. Used to concatenate VPAT Groups A/B/C/D
into unique merged patterns. Setting is used to specify one segment, with up to a maximum of 18 segments.
18b
Select lines for special V-sequence alternation mode for odd lines. Used to concatenate VPAT Groups A/B/C/D
into unique merged patterns. Setting is used to specify one segment, with up to a maximum of 18 segments.
18b
Select lines for special V-sequence alternation mode for odd lines. Used to concatenate VPAT Groups A/B/C/D
into unique merged patterns. Setting is used to specify one segment, with up to a maximum of 18 segments.
1b
Enable special V-pattern to be inserted into one repetition of a VPATA series.
SPC_PAT_EN [0]: set to 1 to enable VPATB to be used as special pattern insertion.
SPC_PAT_EN [1]: set to 1 to enable VPATC to be used as special pattern insertion.
SPC_PAT_EN [2]: set to 1 to enable VPATD to be used as special pattern insertion.
FREEZE2
FREEZE3
FREEZE4
RESUME1
RESUME 2
RESUME3
RESUME4
LASTREPLEN_A
LASTREPLEN_B
LASTREPLEN_C
LASTREPLEN_D
LASTTOG_A
LASTTOG_B
LASTTOG_C
LASTTOG_D
VSEQALT_EN
VALT_MAP
VALTSEL0_EVEN
VALTSEL1_EVEN
VALTSEL0_ODD
VALTSEL1_ODD
SPC_PAT_EN
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9927BBCZRL 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述:
AD9928 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Channel 14-Bit CCD Signal Processor with V-Driver and Precision Timing Generator
AD9928BBCZ 功能描述:IC CCD SIGNAL PROCESSR 128CSPBGA RoHS:是 類別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 產(chǎn)品變化通告:Product Discontinuation 07/Mar/2011 標(biāo)準(zhǔn)包裝:3,000 系列:OMNITUNE™ 類型:調(diào)諧器 應(yīng)用:移動(dòng)電話，手機(jī)，視頻顯示器 安裝類型:表面貼裝 封裝/外殼:65-WFBGA 供應(yīng)商設(shè)備封裝:PG-WFSGA-65 包裝:帶卷 (TR) 其它名稱:SP000365064
AD9928BBCZ-60 制造商:Analog Devices 功能描述:- Trays
AD9928BBCZRL 功能描述:IC CCD SIGNAL PROCESSR 128CSPBGA RoHS:否 類別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 產(chǎn)品變化通告:Product Discontinuation 07/Mar/2011 標(biāo)準(zhǔn)包裝:3,000 系列:OMNITUNE™ 類型:調(diào)諧器 應(yīng)用:移動(dòng)電話，手機(jī)，視頻顯示器 安裝類型:表面貼裝 封裝/外殼:65-WFBGA 供應(yīng)商設(shè)備封裝:PG-WFSGA-65 包裝:帶卷 (TR) 其它名稱:SP000365064
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