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參數資料
| 型號： | AD9927BBCZRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | 14-Bit CCD Signal Processor with V-Driver and Precision TimingTM Generator |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, BGA128 |
| 封裝： | 9 X 9 MM, LEAD FREE, MO-225, CSP_BGA-128 |
| 文件頁數： | 26/100頁 |
| 文件大小： | 784K |
| 代理商： | AD9927BBCZRL |
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AD9927
HBLK Mode 2 Operation
HBLK Mode 2 allows more advanced HBLK pattern operation.
If multiple areas of HCLK pulses that are unevenly spaced apart
from one another are needed, HBLK Mode 2 can be used. Using
a separate set of registers, HBLK Mode 2 can divide the HBLK
region into up to six repeat areas (see Table 11). As shown in
Figure 31, each repeat area shares a common group of toggle
positions, HBLKSTARTA, HBLKSTARTB, and HBLKSTARTC.
However, the number of toggles following each start position
can be unique in each repeat area by using the RAH1REP and
RAH2REP registers. As shown in Figure 30, setting the
RAH1REPA/RAH1REPB/RAH1REPC or RAH2REPA/
RAH2REPB/RAH2REPC registers to 0 masks HCLK groups
from appearing in a particular repeat area. Figure 31 shows only
two repeat areas being used, although six are available. It is possible
to program a separate number of repeat area repetitions for H1
and H2, but generally the same value is used for both H1 and
H2. Figure 31 shows an example of RA0H1REPA/RA0H1REPB/
RA0H1REPC = RA0H2REPA/RA0H2REPB/RA0H2REPC =
RA1H1REPA/RA1H1REPB/RA1H1REPC = RA1H2REPA/
RA1H2REPB/RA1H2REPC = 2.
Rev. 0 | Page 26 of 100
Furthermore, HBLK Mode 2 allows a different HBLK pattern
on even and odd lines. The HBLKSTARTA, HBLKSTARTB, and
HBLKSTARTC registers, as well as the RAH1REPA/RAH1REPB/
RAH1REPC and RAH2REPA/RAH2REPB/RAH2REPC registers,
define operation for the even lines. For separate control of the
odd lines, the HBLKALT_PAT registers specify up to six repeat
areas on the odd lines by reordering the repeat areas used for the
even lines. New patterns are not available, but the order of the
previously defined repeat areas on the even lines can be changed
for the odd lines to accommodate advanced CCD operation.
HORIZONTAL TIMING SEQUENCE EXAMPLE
Figure 32 shows an example CCD layout. The horizontal register
contains 28 dummy pixels, which occur on each line clocked
from the CCD. In the vertical direction, there are 10 optical
black (OB) lines at the front of the readout and two at the back
of the readout. The horizontal direction has four OB pixels in
the front and 48 in the back.
Figure 33 shows the basic sequence layout to be used during the
effective pixel readout. The 48 OB pixels at the end of each line
are used for the CLPOB signals. PBLK is optional and is often
used to blank the digital outputs during the HBLK time. HBLK
is used during the vertical shift interval.
Because PBLK is used to isolate the CDS input (see the Analog
Preblanking section), the PBLK signal should not be used
during CLPOB operation. The change in the offset behavior
that occurs during PBLK impacts the accuracy of the CLPOB
circuitry.
The HBLK, CLPOB, and PBLK parameters are programmed in
the V-sequence registers. More elaborate clamping schemes,
such as adding in a separate sequence to clamp in the entire
shield OB lines, can be used. This requires configuring a
separate V-sequence for clocking out the OB lines.
The CLPMASK registers are also useful for disabling the
CLPOB on a few lines without affecting the setup of the
clamping sequences. It is important that CLPOB be used only
during valid OB pixels. During other portions on the frame
timing, such as vertical blanking or SG line timing, the CCD
does not output valid OB pixels. Any CLPOB pulse that occurs
during this time causes errors in clamping operation and
changes in the black level of the image.
HORIZONTAL CCD REGISTER
EFFECTIVE IMAGEAREA
28 DUMMY PIXELS
48 OB PIXELS
4 OB PIXELS
10 VERTICAL
OB LINES
2 VERTICAL
OB LINES
V
H
0
Figure 32. Example CCD Configuration
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