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參數(shù)資料
| 型號(hào)： | AD9927BBCZRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | 14-Bit CCD Signal Processor with V-Driver and Precision TimingTM Generator |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, BGA128 |
| 封裝： | 9 X 9 MM, LEAD FREE, MO-225, CSP_BGA-128 |
| 文件頁(yè)數(shù)： | 75/100頁(yè) |
| 文件大小： | 784K |
| 代理商： | AD9927BBCZRL |
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AD9927
Rev. 0 | Page 75 of 100
VD
HD
CLI
X
X
X
X
X
X
X
X
3ns MIN
X
X
X
X
X
X
X
X
X
X
X
X
X
3ns MIN
t
CLIDLY
35.5 CYCLES
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
1
2
NOTES
1. EXTERNAL HD FALLING EDGE IS LATCHED BY CLI RISING EDGE, AND THEN LATCHED AGAIN BY SHD INTERNAL FALLING EDGE.
2. INTERNAL H-COUNTER IS ALWAYS RESET 35.5 CLOCK CYCLES AFTER THE INTERNAL HD FALLING EDGE.
3. DEPENDING ON THE VALUE OF SHDLOC, H-COUNTER RESET CAN OCCUR 36 OR 37 CLI CLOCK EDGES AFTER THE EXTERNAL HD FALLING EDGE.
4. SHDLOC = 0 IS SHOWN IN ABOVE EXAMPLE. IN THIS CASE, THE H-COUNTER RESET OCCURS 36 CLI RISING EDGES AFTER HD FALLING EDGE.
5. HD FALLING EDGE SHOULD OCCUR COINCIDENT WITH VD FALLING EDGE (WITHIN SAME CLI CYCLE) OR AFTER VD FALLING EDGE. HD FALLING
EDGE SHOULD NOT OCCUR WITHIN FIVE CLI CYCLES PRIOR TO THE VD FALLING EDGE.
Figure 89. External VD/HD and Internal H-Counter Synchronization, Slave Mode
H-COUNTER
RESET
SHD
INTERNAL
HD
INTERNAL
H-COUNTER
(PIXEL COUNTER)
t
VDHD
0
1
HBLKTOG1
2
HBLKTOG2
3
CLPOB_TOG1
4
CLPOB_TOG2
60
100
103
112
(60 – 36) = 24
(100 – 36) = 64
(103 – 36) = 67
(112 – 36) = 76
MASTER MODE
SLAVE MODE
H1
CLPOB
PIXEL NO.
HD
112
103
100
60
0
1
2
3
4
0
Figure 90. Example of Slave Mode Register Setting to Obtain Desired Toggle Positions
Vertical Toggle Position Placement Near Counter Reset
An additional consideration during the reset of the internal
counters is the vertical toggle position placement. Prior to the
internal counters being reset, there is a region of 36 pixels
during which no toggle positions should be programmed.
As shown in Figure 91, for master mode the last 36 pixels before
the HD falling edge must not be used for toggle position placement
of the V, VSG, SUBCK, HBLK, PBLK, or CLPOB pulses.
Figure 92 shows the same example for slave mode. The same
restriction applies: the last 36 pixels before the counters are
reset cannot be used. However, in slave mode, the counter reset
is delayed with respect to VD/HD placement, so the inhibited
area is different than it is in master mode.
It is recommended that Pixel Location 0 not be used for any of
the toggle positions for the VSG and SUBCK pulses.
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| AD9928 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Channel 14-Bit CCD Signal Processor with V-Driver and Precision Timing Generator |
| AD9928BBCZ | 功能描述:IC CCD SIGNAL PROCESSR 128CSPBGA RoHS:是 類別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 產(chǎn)品變化通告:Product Discontinuation 07/Mar/2011 標(biāo)準(zhǔn)包裝:3,000 系列:OMNITUNE™ 類型:調(diào)諧器 應(yīng)用:移動(dòng)電話，手機(jī)，視頻顯示器 安裝類型:表面貼裝 封裝/外殼:65-WFBGA 供應(yīng)商設(shè)備封裝:PG-WFSGA-65 包裝:帶卷 (TR) 其它名稱:SP000365064 |
| AD9928BBCZ-60 | 制造商:Analog Devices 功能描述:- Trays |
| AD9928BBCZRL | 功能描述:IC CCD SIGNAL PROCESSR 128CSPBGA RoHS:否 類別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 產(chǎn)品變化通告:Product Discontinuation 07/Mar/2011 標(biāo)準(zhǔn)包裝:3,000 系列:OMNITUNE™ 類型:調(diào)諧器 應(yīng)用:移動(dòng)電話，手機(jī)，視頻顯示器 安裝類型:表面貼裝 封裝/外殼:65-WFBGA 供應(yīng)商設(shè)備封裝:PG-WFSGA-65 包裝:帶卷 (TR) 其它名稱:SP000365064 |
| AD9928XBCZ-60 | 功能描述:IC CCD SIGNAL PROCESSOR 制造商:analog devices inc. 系列:- 包裝:托盤 零件狀態(tài):上次購(gòu)買時(shí)間 類型:CCD 信號(hào)處理器，14 位 應(yīng)用:照相機(jī) 安裝類型:表面貼裝 封裝/外殼:128-LFBGA，CSPBGA 供應(yīng)商器件封裝:128-CSPBGA（9x9） 標(biāo)準(zhǔn)包裝:1 |
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