- 您現在的位置：買賣IC網 > PDF目錄373971 > AD9927BBCZRL (ANALOG DEVICES INC) 14-Bit CCD Signal Processor with V-Driver and Precision TimingTM Generator PDF資料下載
參數資料
| 型號： | AD9927BBCZRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | 14-Bit CCD Signal Processor with V-Driver and Precision TimingTM Generator |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, BGA128 |
| 封裝： | 9 X 9 MM, LEAD FREE, MO-225, CSP_BGA-128 |
| 文件頁數： | 72/100頁 |
| 文件大小： | 784K |
| 代理商： | AD9927BBCZRL |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁當前第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁
AD9927
POWER-UP SEQUENCE FOR MASTER MODE
When the AD9927 is powered up, the following sequence is
recommended (refer to Figure 87 for each step). Note that a
SYNC signal is required for master mode operation. If an
external SYNC pulse is not available, it is possible to generate an
internal SYNC event by writing to the SWSYNC register.
Rev. 0 | Page 72 of 100
1.
Turn on the power supplies for AD9927 and start the
master clock, CLI.
Reset the internal AD9927 registers by writing 1 to the
SW_RST register (Address 0x10).
By default, Vertical Outputs V1 to V24 are low. If
necessary, write to the Standby3 output polarity
(Address 0x26) to set different polarities for the vertical
outputs in order to avoid damage to the V-driver
and CCD. Write to Address 0x1C to configure each
V-output as a vertical transfer clock (XV) or sensor
pulse (VSG).
Power-up the V-driver supplies, VH and VL, anytime after
Step 3 is complete to set the proper polarities.
Load the required registers to configure the necessary
vertical timing, horizontal timing, high speed timing,
and shutter timing. Set the recommended start-up
Address 0xD8 to 0x888.
2.
3.
4.
5.
6.
To place the part into normal power operation, write 0x04
to register 0x00. This sets the STANDBY register (AFE
Register Address 0x00, Bits [1:0]) to normal operation and
enables the OB clamp (AFE Register Address 0x00, Bit [2]).
If the CLO output is being used to drive a crystal, also power
up the CLO oscillator by writing 1 to Address 0x15.
By default, the internal timing core is held in a reset state,
with TGCORE_RSTB register = 0. Write 1 to the
TGCORE_RSTB register (Address 0x14) to start the
internal timing core operation. Note if a 2× clock is used
for the CLI input, the CLIDIVIDE register (0x0D) should
be set to 1 before resetting the timing core.
Configure the AD9927 for master mode timing by writing 1
to the MASTER register (Address 0x20).
Write 1 to the OUTCONTROL register (Address 0x11).
This allows the outputs to become active after the next
SYNC rising edge. Normally OUTCONTROL takes effect
after the next VD edge; however, because the part is just
being powered up, there is no VD edge until the rising
edge of the SYNC signal. Write 0xFF8000 to the
VSGSELECT register to properly configure the sensor
gate signals.
10.
Generate a SYNC event. If SYNC is high at power-up,
bring the SYNC input low for a minimum of 100 ns, and
then bring SYNC high again. This causes the internal
counters to reset and starts VD/HD operation. The first
VD/HD edge allows VD-updated register updates to
occur, including OUTCONTROL to enable all outputs.
If a hardware SYNC is not available, the SWSYNC register
(Address 0x13, Bit [14]) can be used to initiate a SYNC event.
7.
8.
9.
相關PDF資料 |
PDF描述 |
|---|---|
| AD9929BBCZ | CCD Signal Processor with Precision Timing Generator |
| AD9929 | CCD Signal Processor with Precision Timing Generator |
| AD9937 | CCD Signal Processor with Precision Timing⑩ Generator |
| AD9937KCP | CCD Signal Processor with Precision Timing⑩ Generator |
| AD9937KCPRL | TVPS00RF-25-35PB W/ PC CONTACT |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9928 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Channel 14-Bit CCD Signal Processor with V-Driver and Precision Timing Generator |
| AD9928BBCZ | 功能描述:IC CCD SIGNAL PROCESSR 128CSPBGA RoHS:是 類別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 產品變化通告:Product Discontinuation 07/Mar/2011 標準包裝:3,000 系列:OMNITUNE™ 類型:調諧器 應用:移動電話，手機，視頻顯示器 安裝類型:表面貼裝 封裝/外殼:65-WFBGA 供應商設備封裝:PG-WFSGA-65 包裝:帶卷 (TR) 其它名稱:SP000365064 |
| AD9928BBCZ-60 | 制造商:Analog Devices 功能描述:- Trays |
| AD9928BBCZRL | 功能描述:IC CCD SIGNAL PROCESSR 128CSPBGA RoHS:否 類別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 產品變化通告:Product Discontinuation 07/Mar/2011 標準包裝:3,000 系列:OMNITUNE™ 類型:調諧器 應用:移動電話，手機，視頻顯示器 安裝類型:表面貼裝 封裝/外殼:65-WFBGA 供應商設備封裝:PG-WFSGA-65 包裝:帶卷 (TR) 其它名稱:SP000365064 |
| AD9928XBCZ-60 | 功能描述:IC CCD SIGNAL PROCESSOR 制造商:analog devices inc. 系列:- 包裝:托盤 零件狀態:上次購買時間 類型:CCD 信號處理器，14 位 應用:照相機 安裝類型:表面貼裝 封裝/外殼:128-LFBGA，CSPBGA 供應商器件封裝:128-CSPBGA（9x9） 標準包裝:1 |
發布緊急采購，3分鐘左右您將得到回復。