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參數(shù)資料
| 型號： | AD9942 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Dual-Channel, 14-Bit CCD Signal Processor with Precision Timing⑩ Core |
| 中文描述： | 雙通道，14位CCD信號處理器核心精確定時⑩ |
| 文件頁數(shù)： | 16/36頁 |
| 文件大小： | 452K |
| 代理商： | AD9942 |
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AD9942
COMPLETE REGISTER LISTING
In Table 8 through Table 16, note the following:
Rev. A | Page 16 of 36
All addresses and default values are expressed in hexadecimal format.
All registers are VD_X/HD_X updated as shown in Figure 14, except for the registers indicated in Table 8, which are SL_X updated.
Each channel is programmed independently using the 5-wire serial interface. Both channels can be programmed with the same
register values by tying the SL_A and SL_B signals together and the SDATA_A and SDATA_B signals together.
Table 8. Updated Registers upon Rising Edge of SL_X
Register
Description
OPRMODE
AFE operation modes
CTLMODE
AFE control modes
SW_RESET
Software reset bit
TGCORE _RSTB
Reset bar signal for internal TG core
PREVENTUPDATE
Prevents update of registers
VDHDEDGE
VD/HD active edge
FIELDVAL
Resets internal field pulse
HBLKRETIME
Retimes the HBLK to internal clock
H1CONTROL
H1 polarity control
RGCONTROL
RG signal control polarity
DRVCONTROL
Drive-strength control
SAMPCONTROL
SHP/SHD sample control
DOUTPHASE
DOUT phase control
Table 9. CHN_A and CHN_B AFE Register Map
Address Data Bit Content
00
[11:0]
01
[9:0]
02
[7:0]
03
[11:0]
04
[17:0]
05
[17:0]
Default (Hex)
4
0
80
4
0
0
Name
OPRMODE
TESTMODE
CLAMP LEVEL
CTLMODE
TESTMODE
TESTMODE
Description
AFE operation modes (see Table 15).
Internal test mode. Should always be set = 0.
CLPOB level.
AFE control modes (see Table 16).
Test operation only. Set = 0.
Test operation only. Set = 0.
Table 10. CHN_A and CHN_B Miscellaneous Register Map
Address Data Bit Content
10
[0]
11
[0]
12
[0]
13
[11:0]
14
[0]
Default (Hex)
0
0
0
0
0
Name
SW_RST
OUT_CONTROL
TGCORE_RSTB
UPDATE
PREVENTUPDA
TE
VDHDEDGE
Description
Software reset.1 = reset all registers to default, then self-clear back to 0.
Output control. 0 = make all dc outputs inactive.
Timing core reset bar. 0 = reset TG core; 1 = resume operation.
Serial update. Sets the line (HD) within the field to update serial data.
Prevents the update of the VD-updated registers. 1 = prevent update.
15
[0]
0
VD/HD active edge.
0 = falling edge triggered; 1 = rising edge triggered.
Field value sync.
0 = next field 0; 1 = next field 1; 2/3 = next field 2.
Retime HBLK to internal H1 clock. Preferred setting is 1. Setting to 1 adds
one cycle delay to HBLK toggle positions.
Internal test mode. Should always be set = 0.
Internal test mode. Should always be set = 0.
Internal test mode. Should always be set = 0.
Internal test mode. Should always be set = 0.
VGA gain control.
16
[1:0]
0
FIELDVAL
17
[0]
0
HBLKRETIME
18
19
1A
E8
[1:0]
[0]
[0]
[2:0]
[11:3]
0
0
0
0
TEST MODE
TEST MODE
TEST MODE
TEST MODE
VGAGAIN
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