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參數(shù)資料
| 型號(hào)： | AD9942 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Dual-Channel, 14-Bit CCD Signal Processor with Precision Timing⑩ Core |
| 中文描述： | 雙通道，14位CCD信號(hào)處理器核心精確定時(shí)⑩ |
| 文件頁(yè)數(shù)： | 5/36頁(yè) |
| 文件大小： | 452K |
| 代理商： | AD9942 |
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AD9942
ANALOG SPECIFICATIONS
T
MIN
to T
MAX
, AVDD_X = DVDD_X = 3.0 V, f
CLI
= 40 MHz, typical timing specifications, unless otherwise noted. X = A, B.
Table 3.
Parameter
Min
Typ
CDS
Gain
0
Allowable CCD Reset Transient
1
500
Max Input Range Before Saturation
1.0
Max CCD Black Pixel Amplitude
±100
Rev. A | Page 5 of 36
Max
Unit
dB
mV
V p-p
mV
Notes
Measured at 12 dB VGA gain
(Typ = 70 mV at 15 dB and 50 mV at 18 dB)
4 LSB/step
Measured at ADC output
Specifications include entire signal chain
12 dB gain applied
AC grounded input, 6 dB gain applied
Measured with step change on supply
VARIABLE GAIN AMPLIFIER (VGA_X)
Max Input Range
Max Output Range
Gain Control Resolution
Gain Monotonicity
Gain Range
Min Gain (Code 0)
Max Gain (Code 511)
CLPOB
Clamp Level Resolution
Clamp Level
Min Clamp Level
Max Clamp Level
CHN_A AND CHN_B ADC
Differential Nonlinearity (DNL)
No Missing Codes
Full-Scale Input Voltage
VOLTAGE REFERENCE
Reference Top Voltage (REFT_X)
Reference Bottom Voltage (REFB_X)
SYSTEM PERFORMANCE
VGA Gain Accuracy
Min Gain (Code 0)
Max Gain (Code 511)
Peak Nonlinearity, 500 mV Input Signal
Total Output Noise
Power Supply Rejection (PSR)
1
Input signal characteristics defined as follows:
1.0
2.0
1.0
0.5
17.5
512
Guaranteed
0
18
256
0
1023
± 0.5
Guaranteed
2.0
2.0
1.0
0
18
0.15
3
50
+1.0
+0.5
18.5
V p-p
V p-p
Steps
dB
dB
Steps
LSB
LSB
LSB
V
V
V
dB
dB
%
LSB rms
dB
0
OPTI100mV MAX
RE500mV TYP
INPUT 1V MAX
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