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參數資料
| 型號： | AD9942 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Dual-Channel, 14-Bit CCD Signal Processor with Precision Timing⑩ Core |
| 中文描述： | 雙通道，14位CCD信號處理器核心精確定時⑩ |
| 文件頁數： | 26/36頁 |
| 文件大小： | 452K |
| 代理商： | AD9942 |
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AD9942
CHANNEL A AND CHANNEL B POWER-UP PROCEDURE
When the AD9942 is powered up, the following sequence is
recommended for Channel A and Channel B (see Figure 27 for
each step).
Rev. A | Page 26 of 36
1.
Turn on the power supplies for the AD9942.
2.
Apply the master clock input, CLI_X, VD_X, and HD_X.
3.
Although the AD9942 contains an on-chip power-on reset,
a software reset of the internal registers is recommended.
Write a 1 to the SW_RST register (Address 0x10), which
resets all the internal registers to their default values. This
bit is self-clearing and is automatically reset to 0.
4.
Reset the
Precision Timing
core by writing a 0 to the
TGCORE_RSTB register (Address 0x12), then write a l to
the TGCORE_RSTB register. This starts the internal
timing core operation.
5.
Write a 1 to the PREVENTUPDATE register (Address 0x14).
This prevents an update of the serial register data.
6.
Write to the desired registers to configure high speed
timing and horizontal timing.
7.
Write a 3 to the [7:6] TESTMODE register (Address 0x00).
See Table 15.
8.
Write a 1 to the OUT_CONTROL register (Address 0x11).
This allows the outputs to become active after the next
VD_X/HD_X rising edge.
9.
Write a 0 to the PREVENTUPDATE register (Address 0x14).
This allows the serial information to be updated at the
next VD_X/HD_X falling edge. The next VD_X/HD_X
falling edge allows register updates, including updates of
OUT_CONTROL, to occur which enables all clock outputs.
0
VDD
(INPUT)
SERIAL
WRITES
VD_X
(OUTPUT)
1H
ODD FIELD
EVEN FIELD
...
...
DIGITAL
OUTPUTS
CLOCKS ACTIVE WHEN OUT_CONTROL REGISTER IS
UPDATED AT VD/HD EDGE
H1X/H3X, RG_X
H2X/H4X
t
PWR
CLI_X
(INPUT)
HD_X
(OUTPUT)
1V
...
...
1
2
2
3
4
5
6
7
8
9
Figure 27. Recommended Power-Up Sequence
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| AD9942BBCZ | Dual-Channel, 14-Bit CCD Signal Processor with Precision Timing⑩ Core |
| AD9942BBCZRL | Dual-Channel, 14-Bit CCD Signal Processor with Precision Timing⑩ Core |
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相關代理商/技術參數 |
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| AD9942BBCZ | 功能描述:IC PROCESSOR SGNL 14B 100CSPBGA RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調幀器 應用:數據傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應商設備封裝:400-PBGA（27x27） 包裝:散裝 |
| AD9942BBCZRL | 功能描述:IC PROCESSOR SGNL 14B 100CSPBGA RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調幀器 應用:數據傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應商設備封裝:400-PBGA（27x27） 包裝:散裝 |
| AD9943 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Complete 10-Bit and 12-Bit, 25 MHz CCD Signal Processors |
| AD9943KCP | 制造商:Analog Devices 功能描述:AFE Video 1ADC 10-Bit 3V 32-Pin LFCSP EP 制造商:Rochester Electronics LLC 功能描述:10 BIT 25 MHZ LOW COST ANALOG FRONT END - Bulk |
| AD9943KCPRL | 制造商:Analog Devices 功能描述:AFE Video 1ADC 10-Bit 3V 32-Pin LFCSP EP T/R |
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