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參數資料
| 型號： | AD9942 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Dual-Channel, 14-Bit CCD Signal Processor with Precision Timing⑩ Core |
| 中文描述： | 雙通道，14位CCD信號處理器核心精確定時⑩ |
| 文件頁數： | 9/36頁 |
| 文件大小： | 452K |
| 代理商： | AD9942 |
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AD9942
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Rev. A | Page 9 of 36
0
1
A1 CORNER
INDEX AREA
2
3
4
5
6
7
8
9 10
A
B
C
D
E
F
G
H
J
K
AD9942
TOP VIEW
(Not to Scale)
Figure 2. Pin Configuration
Table 7. Pin Function Descriptions
Ball Location
B2
C2
D2
C1
D1
A1
F4
F3
D4
D3
B4
J2
K3
E3
E4
C3
C4
B3
A4
B1
A2
F2
F1
E2
E1
B8
C8
D8
C7
D7
A7
F10
F9
D10
Mnemonic
SL_A
SDATA_A
SCK_A
REFT_A
REFB_A
CCDIN_A
H1A
H2A
H3A
H4A
RG_A
DRVSS_A
DRVDD_A
HVSS_A
HVDD_A
RGVSS_A
RGVDD_A
TCVSS_A
TCVDD_A
AVSS_A
AVDD_A
DVSS_A
DVDD_A
VD_A
HD_A
SL_B
SDATA_B
SCK_B
REFT_B
REFB_B
CCDIN_B
H1B
H2B
H3B
Type
1
DI
DI
DI
AO
AO
AI
DO
DO
DO
DO
DO
P
P
P
P
P
P
P
P
P
P
P
P
DI
DI
DI
DI
DI
AO
AO
AI
DO
DO
DO
Description
6-Wire Serial Load for Channel A
6-Wire Serial Data for Channel A
6-Wire Serial Clock for Channel A
Reference Top Decoupling for Channel A (decouple with 1.0 μF to AVSS_A)
Reference Bottom Decoupling for Channel A (decouple with 1.0 μF to AVSS_A)
Analog Input for Channel A CCD Signal (connect through series 0.1 μF capacitor)
CCD Horizontal Clock 1 for Channel A
CCD Horizontal Clock 2 for Channel A
CCD Horizontal Clock 3 for Channel A
CCD Horizontal Clock 4 for Channel A
CCD Reset Gate Clock for Channel A
Digital Driver Ground for Channel A
Digital Driver Supply for Channel A
H1A to H4A Driver Ground for Channel A
H1A to H4A Driver Supply for Channel A
RG_A Driver Ground for Channel A
RG_A Driver Supply for Channel A
Analog Ground for Channel A Timing Core
Analog Supply for Channel A Timing Core
Analog Ground for Channel A
Analog Ground for Channel A
Digital Ground for Channel A
Digital Supply for Channel A
Vertical Sync Pulse for Channel A
Horizontal Sync Pulse for Channel A
6-Wire Serial Load for Channel B
6-Wire Serial Data for Channel B
6-Wire Serial Clock for Channel B
Reference Top Decoupling for Channel B (decouple with 1.0 μF to AVSS_B)
Reference Bottom Decoupling for Channel B (decouple with 1.0 μF to AVSS_B)
Analog Input for Channel B CCD Signal (connect through series 0.1 μF capacitor)
CCD Horizontal Clock 1 for Channel B
CCD Horizontal Clock 2 for Channel B
CCD Horizontal Clock 3 for Channel B
相關PDF資料 |
PDF描述 |
|---|---|
| AD9942BBCZ | Dual-Channel, 14-Bit CCD Signal Processor with Precision Timing⑩ Core |
| AD9942BBCZRL | Dual-Channel, 14-Bit CCD Signal Processor with Precision Timing⑩ Core |
| AD9943 | Label Printer Tape RoHS Compliant: NA |
| AD9944 | Complete 10-Bit and 12-Bit, 25 MHz CCD Signal Processors |
| AD9943KCPZRL | Complete 10-Bit and 12-Bit, 25 MHz CCD Signal Processors |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9942BBCZ | 功能描述:IC PROCESSOR SGNL 14B 100CSPBGA RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調幀器 應用:數據傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應商設備封裝:400-PBGA（27x27） 包裝:散裝 |
| AD9942BBCZRL | 功能描述:IC PROCESSOR SGNL 14B 100CSPBGA RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調幀器 應用:數據傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應商設備封裝:400-PBGA（27x27） 包裝:散裝 |
| AD9943 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Complete 10-Bit and 12-Bit, 25 MHz CCD Signal Processors |
| AD9943KCP | 制造商:Analog Devices 功能描述:AFE Video 1ADC 10-Bit 3V 32-Pin LFCSP EP 制造商:Rochester Electronics LLC 功能描述:10 BIT 25 MHZ LOW COST ANALOG FRONT END - Bulk |
| AD9943KCPRL | 制造商:Analog Devices 功能描述:AFE Video 1ADC 10-Bit 3V 32-Pin LFCSP EP T/R |
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