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參數(shù)資料
| 型號： | AD9942 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Dual-Channel, 14-Bit CCD Signal Processor with Precision Timing⑩ Core |
| 中文描述： | 雙通道，14位CCD信號處理器核心精確定時⑩ |
| 文件頁數(shù)： | 24/36頁 |
| 文件大小： | 452K |
| 代理商： | AD9942 |
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AD9942
CHANNEL A AND CHANNEL B SPECIAL HBLK PATTERNS
Six toggle positions are available for HBLK. Typically, only two
of the toggle positions are used to generate the standard HBLK
interval. However, the additional toggle positions can be used to
generate special HBLK patterns, as shown in Figure 24. The
pattern in this example uses all six toggle positions to generate
two extra groups of pulses during the HBLK interval. By
changing the toggle positions, different patterns can be created.
Rev. A | Page 24 of 36
HORIZONTAL SEQUENCE CONTROL
The AD9942 uses sequence change positions (SCPs) and
sequence pointers (SPTRs) to organize the individual horizontal
sequences. Up to four SCPs are available to divide the readout
into four separate regions, as shown in Figure 25. The SCP0 is
always hard-coded to Line 0, and SCP1 to SCP3 are register
programmable. During each region bounded by the SCP, the
SPTR registers designate which sequence is used by each signal.
CLPOB, PBLK, and HBLK each have a separate set of SCPs. For
example, CLPOBSCP1 defines Region 0 for CLPOB, and in that
region any of the four CLPOB sequences can be selected with
the CLPOBSPTR register. The next SCP defines a new region,
in which each signal can be assigned to a different individual se-
quence. The sequence control registers are detailed in Table 21.
HBLK
SPECIAL H-BLANK PATTERN IS CREATED USING MULTIPLE HBLK TOGGLE POSITIONS.
H1X/H3X
H2X/H4X
TOG1
TOG2
TOG3
TOG4
TOG5
TOG6
0
Figure 24. Generating Special HBLK Patterns
UP TO FOUR INDIVIDUAL HORIZONTAL CLAMP AND BLANKING REGIONS MAY BE
PROGRAMMED WITHIN A SINGLE FIELD, USING THE SEQUENCE CHANGE POSITIONS.
SEQUENCE CHANGE OF POSITION 1
SEQUENCE CHANGE OF POSITION 2
SEQUENCE CHANGE OF POSITION 3
SINGLE FIELD (1 VD INTERVAL)
CLAMP AND PBLK SEQUENCE REGION 0
SEQUENCE CHANGE OF POSITION 0
(V COUNTER = 0)
CLAMP AND PBLK SEQUENCE REGION 3
CLAMP AND PBLK SEQUENCE REGION 2
CLAMP AND PBLK SEQUENCE REGION 1
0
Figure 25. CLPOB and PBLK Sequence Flexibility
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9942BBCZ | Dual-Channel, 14-Bit CCD Signal Processor with Precision Timing⑩ Core |
| AD9942BBCZRL | Dual-Channel, 14-Bit CCD Signal Processor with Precision Timing⑩ Core |
| AD9943 | Label Printer Tape RoHS Compliant: NA |
| AD9944 | Complete 10-Bit and 12-Bit, 25 MHz CCD Signal Processors |
| AD9943KCPZRL | Complete 10-Bit and 12-Bit, 25 MHz CCD Signal Processors |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9942BBCZ | 功能描述:IC PROCESSOR SGNL 14B 100CSPBGA RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| AD9942BBCZRL | 功能描述:IC PROCESSOR SGNL 14B 100CSPBGA RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| AD9943 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Complete 10-Bit and 12-Bit, 25 MHz CCD Signal Processors |
| AD9943KCP | 制造商:Analog Devices 功能描述:AFE Video 1ADC 10-Bit 3V 32-Pin LFCSP EP 制造商:Rochester Electronics LLC 功能描述:10 BIT 25 MHZ LOW COST ANALOG FRONT END - Bulk |
| AD9943KCPRL | 制造商:Analog Devices 功能描述:AFE Video 1ADC 10-Bit 3V 32-Pin LFCSP EP T/R |
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