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參數資料
| 型號： | AD9942BBCZRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | Dual-Channel, 14-Bit CCD Signal Processor with Precision Timing⑩ Core |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA100 |
| 封裝： | 9 X 9 MM, LEAD FREE, MO-205AB, CSPBGA-100 |
| 文件頁數： | 15/36頁 |
| 文件大小： | 452K |
| 代理商： | AD9942BBCZRL |
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AD9942
SERIAL INTERFACE TIMING
All of the AD9942 internal registers are accessed through a
6-wire serial interface. Each register consists of an 8-bit address
and a 24-bit data-word. Both the 8-bit address and the 24-bit
data-word are written starting with the LSB. To write to each
register, a 32-bit operation is required, as shown in Figure 14.
Although many registers are less than 24 bits wide, all 24 bits
must be written for each register. If the register is only 16 bits
wide, then the upper 8 bits can be filled with 0s during the serial
write operation. If fewer than 24 bits are written, the register is
not updated with new data.
Rev. A | Page 15 of 36
Figure 15 shows a more efficient way to write to the registers by
using the AD9942 address auto-increment capability. In this
method, the lowest desired address is written first, followed by
multiple 24-bit data-words. Each new 24-bit data-word is
written automatically to the next highest register address. By
eliminating the need to write each 8-bit address, faster register
loading is achieved. The address auto-increment function can
be used, starting with any register location, to write to as few as
two registers or to as many as the entire register space.
0
SDATA
_X
A0
A1
A2
A4
A5
A6
A7
D0
D1
D2
D3
D21
D22
D23
SCK
_X
SL
_X
A3
NOTES
1. X = A, B.
2. INDIVIDUAL SDATA_X BITS ARE LATCHED UPON SCK_X RISING EDGES.
3. ALL 32 BITS MUST BE WRITTEN: 8 BITS FORADDRESS AND 24 BITS FOR DATA.
4. IF THE REGISTER LENGTH IS <24 BITS, THEN DON’T CARE BITS MUST BE USEDTO COMPLETE THE 24-BIT DATA LENGTH.
5. NEW DATA IS UPDATED AT EITHER THE SL_X RISING EDGE ORAT THE HD_X FALLING EDGEAFTER THE NEXT VD_X FALLING EDGE.
6. VD_X/HD_X UPDATE POSITION CAN BE DELAYED TO ANY HD_X FALLING EDGE IN THE FIELD USING THE UPDATE REGISTER.
Figure 14. Serial Write Operation
VD
_X
SL UPDATED
VD/HD UPDATED
HD
_X
...
...
...
...
...
8-BIT ADDRESS
24-BIT DATA
1
32
2
3
4
5
6
7
8
9
10
11
12
30
31
t
LS
t
DS
t
DH
t
LH
0
SDATA_X
A0
A1
A2
A4
A5
A6
A7
D0
D1
D22
D23
SCK_X
SL_X
A3
NOTES
1. X = A, B.
2. MULTIPLE SEQUENTIAL REGISTERS CAN BE LOADED CONTINUOUSLY.
3. THE FIRST (LOWEST ADDRESS) REGISTER ADDRESS IS WRITTEN, FOLLOWED BY MULTIPLE 24-BIT DATA-WORDS.
4. THE ADDRESS AUTOMATICALLY INCREMENTS WITH EACH 24-BIT DATA-WORD (ALL 24 BITS MUST BE WRITTEN).
5. SL_X IS HELD LOW UNTIL THE LAST DESIRED REGISTER HAS BEEN LOADED.
6. NEW DATA IS UPDATED AT EITHER THE SL RISING EDGE OR AT THE HD FALLING EDGE AFTER THE NEXT VD FALLING EDGE.
D0
D1
D22
D23
D0
...
...
...
DATA FOR STARTING
REGISTER ADDRESS
...
DATA FOR NEXT
REGISTER ADDRESS
...
D2
D1
...
...
...
...
1
32
2
3
4
5
6
7
8
9
10
31
34
33
56
55
58
57
59
Figure 15. Continuous Serial Write Operation
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