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參數資料
| 型號： | AD9942BBCZRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | Dual-Channel, 14-Bit CCD Signal Processor with Precision Timing⑩ Core |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA100 |
| 封裝： | 9 X 9 MM, LEAD FREE, MO-205AB, CSPBGA-100 |
| 文件頁數： | 17/36頁 |
| 文件大?。?/td> | 452K |
| 代理商： | AD9942BBCZRL |
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AD9942
Table 11. CHN_A and CHN_B CLPOB Register Map
Address Data Bit Content
20
[3:0]
21
[23:0]
22
[23:0]
23
[23:0]
24
[23:0]
25
[7:0]
26
[11:0]
27
[11:0]
28
[11:0]
Rev. A | Page 17 of 36
Default (Hex)
F
FFFFFF
FFFFFF
FFFFFF
FFFFFF
00
FFF
FFF
FFF
Name
CLPOBPOL
CLPOBTOG_0
CLPOBTOG_1
CLPOBTOG_2
CLPOBTOG_3
CLPOBSPTR
CLPOBSCP1
CLPOBSCP2
CLPOBSCP3
Description (the CLPOBSCP0 Always Starts at Line 0)
Start polarities for CLPOB Sequences 0, 1, 2, and 3.
Sequence 0. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
Sequence 1. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
Sequence 2. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
Sequence 3. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
CLPOB sequence pointers for Region 0 [1:0], 1 [3:2], 2 [5:4], and 3 [7:6].
CLPOB sequence—Change Position 1.
CLPOB sequence—Change Position 2.
CLPOB sequence—Change Position 3.
Table 12. PBLK Register Map
Address Data Bit Content
30
[3:0]
31
[23:0]
32
[23:0]
33
[23:0]
34
[23:0]
35
[7:0]
36
[11:0]
37
[11:0]
38
[11:0]
Default (Hex)
F
FFFFFF
FFFFFF
FFFFFF
FFFFFF
00
FFF
FFF
FFF
Name
PBLKPOL
PBLKTOG_0
PBLKTOG_1
PBLKTOG_2
PBLKTOG_3
PBLKSPTR
PBLKSCP1
PBLKSCP2
PBLKSCP3
Description (the PBLKSCP0 Always Starts at Line 0)
Start polarities for PBLK Sequences 0, 1, 2, and 3.
Sequence 0. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
Sequence 1. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
Sequence 2. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
Sequence 3. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
PBLK Sequence Pointers for Region 0 [1:0], 1 [3:2], 2 [5:4], and 3 [7:6].
PBLK sequence—Change Position 1.
PBLK sequence—Change Position 2.
PBLK sequence—Change Position 3.
Table 13. HBLK Register Map
Address Data Bit Content
40
[0]
41
[0]
42
[0]
43
[3:0]
44
[23:0]
45
[23:0]
46
[23:0]
47
[23:0]
48
[23:0]
49
[23:0]
4A
[23:0]
4B
[23:0]
4C
[23:0]
4D
[23:0]
4E
[23:0]
4F
[23:0]
50
[7:0]
51
[11:0]
52
[11:0]
53
[11:0]
Default (Hex)
0
0
1
F
FFFFFF
FFFFFF
FFFFFF
FFFFFF
FFFFFF
FFFFFF
FFFFFF
FFFFFF
FFFFFF
FFFFFF
FFFFFF
FFFFFF
00
FFF
FFF
FFF
Name
TESTMODE
TESTMODE
TESTMODE
HBLKMASK
HBLKTOG12_0
HBLKTOG34_0
HBLKTOG56_0
HBLKTOG12_1
HBLKTOG34_1
HBLKTOG56_1
HBLKTOG12_2
HBLKTOG34_2
HBLKTOG56_2
HBLKTOG12_3
HBLKTOG34_3
HBLKTOG56_3
HBLKSPTR
HBLKSCP1
HBLKSCP2
HBLKSCP3
Description (the HBLKSCP0 Always Starts at Line 0)
Test mode. Always set = 0 if accessed.
Test mode. Always set = 0 if accessed.
Test mode. Always set = 1 if accessed.
HBLK internal masking polarity. 0 = mask H1 low; 1 = mask H1 high.
Sequence 0. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
Sequence 0. Toggle Position 3 [11:0] and Toggle Position 4 [23:12].
Sequence 0. Toggle Position 5 [11:0] and Toggle Position 6 [23:12].
Sequence 1. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
Sequence 1. Toggle Position 3 [11:0] and Toggle Position 4 [23:12].
Sequence 1. Toggle Position 5 [11:0] and Toggle Position 6 [23:12].
Sequence 2. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
Sequence 2. Toggle Position 3 [11:0] and Toggle Position 4 [23:12].
Sequence 2. Toggle Position 5 [11:0] and Toggle Position 6 [23:12].
Sequence 3. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
Sequence 3. Toggle Position 3 [11:0] and Toggle Position 4 [23:12].
Sequence 3. Toggle Position 5 [11:0] and Toggle Position 6 [23:12].
HBLK sequence pointers for Region 0 [1:0], 1 [3:2], 2 [5:4], and 3 [7:6].
HBLK sequence—Change Position 1.
HBLK sequence—Change Position 2.
HBLK sequence—Change Position 3.
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