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參數資料
| 型號： | AD9942BBCZRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | Dual-Channel, 14-Bit CCD Signal Processor with Precision Timing⑩ Core |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA100 |
| 封裝： | 9 X 9 MM, LEAD FREE, MO-205AB, CSPBGA-100 |
| 文件頁數： | 31/36頁 |
| 文件大小： | 452K |
| 代理商： | AD9942BBCZRL |
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AD9942
DRIVING THE CLI INPUT
The AD9942 CLI can be used in two configurations, depending
on the application. Figure 31 shows a typical dc-coupled input
from the master clock source. When the dc-coupled technique
is used, the master clock signal should be at standard 3 V CMOS
logic levels. As shown in Figure 32, a 1000 pF ac coupling
capacitor can be used between the clock source and the CLI input.
In this configuration, the CLI input performs a self-bias to the
proper dc voltage level of approximately 1.4 V. When the ac-
coupled technique is used, the master clock signal can be as
low as ±500 mV in amplitude.
Rev. A | Page 31 of 36
HORIZONTAL TIMING SEQUENCE EXAMPLE
Figure 33 shows an example CCD configuration. The horizontal
register contains 28 dummy pixels, which occur on each line
clocked from the CCD. In the vertical direction, there are
10 OB lines at the front of the readout and 2 at the back of the
readout. The horizontal direction has 4 OB pixels in the front
and 48 in the back.
To configure the AD9942 horizontal signals for this CCD, three
sequences can be used. Figure 34 shows the first sequence to be
used during vertical blanking. During this time, there are no
valid OB pixels from the sensor, so the CLPOB signal is not
used. PBLK can be enabled during this time because no valid
data is available.
Figure 35 shows the recommended sequence for the vertical OB
interval. The clamp signals are used across the whole lines to
stabilize the clamp loop of the AD9942.
Figure 36 shows the recommended sequence for the effective
pixel readout. The 48 OB pixels at the end of each line are used
for the CLPOB signal.
0
CLI_X
AD9942
ASIC
MASTER CLOCK
Figure 31. CLI Connection, DC-Coupled
0
LPF
1nF
CLI_X
AD9942
ASIC
MASTER CLOCK
Figure 32. CLI Connection, AC-Coupled
0
V
H
USE SEQUENCE 2
USE SEQUENCE 3
SEQUENCE 2 (OPTIONAL)
HORIZONTAL CCD REGISTER
EFFECTIVE IMAGE AREA
28 DUMMY PIXELS
48 OB PIXELS
4 OB PIXELS
10 VERTICAL OB LINES
2 VERTICAL OB LINES
Figure 33. Example CCD Configuration
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