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| 型號(hào)： | AD9942BBCZRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類(lèi)： | 消費(fèi)家電 |
| 英文描述： | Dual-Channel, 14-Bit CCD Signal Processor with Precision Timing⑩ Core |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA100 |
| 封裝： | 9 X 9 MM, LEAD FREE, MO-205AB, CSPBGA-100 |
| 文件頁(yè)數(shù)： | 19/36頁(yè) |
| 文件大小： | 452K |
| 代理商： | AD9942BBCZRL |
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AD9942
CHANNEL A AND CHANNEL B
PRECISION TIMING
HIGH SPEED TIMING GENERATION
The AD9942 generates flexible, high speed timing signals using
the
Precision Timing
core for both channels. This core is the
foundation for generating the timing used for both the CCD
and the AFE, the reset gate RG_X, the horizontal drivers H1X
to H4X, and the SHP/SHD sample clocks. A unique architecture
makes it routine for the system designer to optimize image
quality by providing precise control over the horizontal CCD
readout and the AFE correlated double sampling.
Rev. A | Page 19 of 36
TIMING RESOLUTION
The
Precision Timing
core uses a 1× master clock input (CLI) as
a reference. This clock should be the same as the CCD pixel
clock frequency. Figure 16 illustrates how the internal timing
core divides the master clock period into 48 steps or edge
positions. Therefore, the edge resolution of the
Precision Timing
core is (t
CLI
/48). For more information on using the CLI input,
see the Applications Information section.
HIGH SPEED CLOCK PROGRAMMABILITY
Figure 17 shows how the high speed clocks, RG_X, H1X to
H4X, SHP, and SHD, are generated. The RG_X pulse has
programmable rising and falling edges and can be inverted
using the polarity control. The horizontal clock, H1, has
programmable rising and falling edges and polarity control.
The H2 clock is always the inverse of the H1 clock. Table 17 sum-
marizes the high speed timing registers and their parameters.
Each edge location setting is six bits wide, but only 48 valid edge
locations are available. Therefore, the register values are
mapped into four quadrants, with each quadrant containing
12 edge locations. Table 18 shows the correct register values for
the corresponding edge locations.
0
NOTES
1. PIXEL CLOCK PERIOD IS DIVIDED INTO 48 POSITIONS, PROVIDING FINE EDGE RESOLUTION FOR HIGH SPEED CLOCKS.
2. THERE IS A FIXED DELAY FROM THE CLI_X INPUT TO THE INTERNAL PIXEL PERIOD POSITIONS (
t
CLIDLY
= 6ns TYP).
P[0]
P[48] = P[0]
P[12]
P[24]
P[36]
1 PIXEL
PERIOD
...
...
CLI_X
t
CLIDLY
POSITION
Figure 16. High Speed Clock Resolution from CLI
0
H1X/H3X
H2X/H4X
CCD SIGNAL
RG_X
1
2
3
4
5
6
PROGRAMMABLE CLOCK POSITIONS:
1
RG_X RISING EDGE.
2
RG_X FALLING EDGE.
3
SHP SAMPLE LOCATION.
4
SHD SAMPLE LOCATION.
5
H1X/H3X RISING EDGE POSITION.
6
H1X/H3X FALLING EDGE POSITION (H2X/H4X ARE INVERSE OF H1X/H3X).
Figure 17. High Speed Clock Programmable Locations
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PDF描述 |
|---|---|
| AD9943 | Label Printer Tape RoHS Compliant: NA |
| AD9944 | Complete 10-Bit and 12-Bit, 25 MHz CCD Signal Processors |
| AD9943KCPZRL | Complete 10-Bit and 12-Bit, 25 MHz CCD Signal Processors |
| AD9944KCP | Complete 10-Bit and 12-Bit, 25 MHz CCD Signal Processors |
| AD9944KCPRL | Complete 10-Bit and 12-Bit, 25 MHz CCD Signal Processors |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9943 | 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:Complete 10-Bit and 12-Bit, 25 MHz CCD Signal Processors |
| AD9943KCP | 制造商:Analog Devices 功能描述:AFE Video 1ADC 10-Bit 3V 32-Pin LFCSP EP 制造商:Rochester Electronics LLC 功能描述:10 BIT 25 MHZ LOW COST ANALOG FRONT END - Bulk |
| AD9943KCPRL | 制造商:Analog Devices 功能描述:AFE Video 1ADC 10-Bit 3V 32-Pin LFCSP EP T/R |
| AD9943KCPZ | 功能描述:IC CCD SIGNAL PROCESSOR 32-LFCSP RoHS:是 類(lèi)別:集成電路 (IC) >> 接口 - 傳感器和探測(cè)器接口 系列:- 其它有關(guān)文件:Automotive Product Guide 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:74 系列:- 類(lèi)型:觸控式傳感器 輸入類(lèi)型:數(shù)字 輸出類(lèi)型:數(shù)字 接口:JTAG，串行 電流 - 電源:100µA 安裝類(lèi)型:表面貼裝 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:20-TSSOP 包裝:管件 |
| AD9943KCPZ1 | 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:Complete 10-Bit and 12-Bit, 25 MHz CCD Signal Processors |
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