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參數資料
| 型號： | AD9942BBCZRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | Dual-Channel, 14-Bit CCD Signal Processor with Precision Timing⑩ Core |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA100 |
| 封裝： | 9 X 9 MM, LEAD FREE, MO-205AB, CSPBGA-100 |
| 文件頁數： | 18/36頁 |
| 文件大小： | 452K |
| 代理商： | AD9942BBCZRL |
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AD9942
Table 14. CHN_A and CHN_B H1 to H4, RG, SHP, SHD Register Map
Address Data Bit Content
Default (Hex)
60
[12:0]
01001
Rev. A | Page 18 of 36
Name
H1CONTROL
Description
H1 signal control. Polarity [0] (0 = inversion; 1 = no inversion).
H1 positive edge location [6:1].
H1 negative edge location [12:7].
RG signal control. Polarity [0] (0 = inversion; 1 = no inversion).
RG positive-edge location [6:1].
RG negative-edge location [12:7].
Drive-strength control for H1X [2:0], H2X [5:3], H3X [8:6], H4X [11:9],
and RG_X [14:12].
Drive-current values: 0 = off, 1 = 4.3 mA, 2 = 8.6 mA, 3 = 12.9 mA,
4 = 17.2 mA, 5 = 21.5 mA, 6 = 25.8 mA, 7 = 30.1 mA.
SHP/SHD sample control. SHP sampling location [5:0]. SHD sampling
location [11:6].
DOUT phase control.
61
[12:0]
00801
RGCONTROL
62
[14:0]
0
DRVCONTROL
63
[11:0]
00024
SAMPCONTROL
64
[5:0]
0
DOUTPHASE
Table 15. CHN_A and CHN_B AFE Operation Register Detail
Address Data Bit Content
Default (Hex)
00
[1:0]
0
[2]
1
[3]
0
[4]
0
[5]
0
[7:6]
0
[8]
0
[9]
0
[11:10]
0
Name
PWRDOWN
CLPENABLE
CLPSPEED
FASTUPDATE
PBLK_LVL
TEST MODE
DCBYP
TESTMODE
TESTMODE
Description
0 = normal operation; 1 = reference standby; 2/3 = total power-down.
0 = disable CLPOB; 1 = enable CLPOB.
0 = select normal CLPOB settling; 1 = select fast CLPOB settling.
0 = ignore VGA update; 1 = very fast clamping when VGA is updated.
DOUT value during PBLK; 0 = blank to zero; 1 = blank to clamp level.
Internal test mode. Should always be set = 3.
0 = enable dc restore circuit; 1 = bypass dc restore circuit during PBLK.
Test operation only. Set = 0.
Test operation only. Set = 0.
Table 16. CHN_A and CHN_B AFE Control Register Detail
Address Data Bit Content
03
[1:0]
[2]
[3]
[4]
[5]
Default (Hex)
0
1
0
0
0
Name
TESTMODE
TESTMODE
DOUTDISABLE
DOUTLATCH
GRAYENCODE
Description
Test operation only. Set = 0.
Test operation only. Set = 0.
0 = data outputs are driven; 1 = data outputs are three-stated.
0 = latch data outputs with DOUT phase; 1 = output latch transparent.
0 = binary encode data outputs; 1 = gray encode data outputs.
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