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參數資料
| 型號： | AD9942BBCZRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | Dual-Channel, 14-Bit CCD Signal Processor with Precision Timing⑩ Core |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA100 |
| 封裝： | 9 X 9 MM, LEAD FREE, MO-205AB, CSPBGA-100 |
| 文件頁數： | 27/36頁 |
| 文件大小： | 452K |
| 代理商： | AD9942BBCZRL |
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AD9942
CHANNEL A AND CHANNEL B ANALOG FRONT END OPERATION
The AD9942 signal processing chain is shown in Figure 28.
Each processing step is essential for achieving a high quality
image from the raw CCD pixel data.
Rev. A | Page 27 of 36
DC RESTORE
To reduce the large dc offset of the CCD output signal, a dc
restore circuit is used with an external 0.1 μF series coupling
capacitor. This restores the dc level of the CCDIN_X signal to
approximately 1.5 V to be compatible with the 3 V supply
voltage of the AD9942.
CORRELATED DOUBLE SAMPLER
The CDS circuit samples each CCD pixel twice to extract the
video information and reject low frequency noise. The timing
shown in Figure 17 illustrates how the two internally generated
CDS clocks, SHP and SHD, are used to sample the reference
level and the CCD signal level, respectively. The placement of
the SHP and SHD sampling edges is determined by the setting
of the SAMPCONTROL register located at Address 0x63.
Placement of these two clock signals is critical for achieving the
best performance from the CCD.
0
CCDIN_X
DIGITAL
FILTER
CLPOB
DC RESTORE
OPTICAL BLACK
CLAMP
ADC
DAC
8
CDS
INTERNAL
V
REF
2V FULL SCALE
0dB ~ 18dB
SHP
SHD
VGA1
1.5V
OUTPUT
DATA
LATCH
REFT_X
REFB_X
DOUT
PHASE
PBLK
1.0V
2.0V
DOUT
AD9942
1.0μF 1.0μF
1.0μF
VGA GAIN
REGISTERS
CLAMP LEVEL
REGISTER
14
CLPOB PBLK
V-H
TIMING
GENERATION
SHP
SHD
DOUT
PHASE
PRECISION
GETIMING
Figure 28. Channel A and Channel B Analog Front End Functional Block Diagram
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