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參數(shù)資料
| 型號： | AD9942BBCZRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | Dual-Channel, 14-Bit CCD Signal Processor with Precision Timing⑩ Core |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA100 |
| 封裝： | 9 X 9 MM, LEAD FREE, MO-205AB, CSPBGA-100 |
| 文件頁數(shù)： | 29/36頁 |
| 文件大小： | 452K |
| 代理商： | AD9942BBCZRL |
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AD9942
APPLICATIONS INFORMATION
CIRCUIT CONFIGURATION
The AD9942 recommended circuit configuration is shown in
Figure 30. Achieving good image quality from the AD9942
requires careful attention to the printed circuit board (PCB)
layout. All signals should be routed to maintain low noise
performance. The CCD_A and CCD_B output signals should
be directly routed to Pins A1 and A7, respectively, through a
0.1 μF capacitor. The master clock, CLI_X, should be carefully
routed to Pins A3 and A9 to minimize interference with the
CCDIN_X, REFT_X, and REFB_X signals.
Rev. A | Page 29 of 36
The digital outputs and clock inputs should be connected to the
digital ASIC away from the analog and CCD clock signals.
Placing series resistors close to the digital output pins may help
to reduce digital code transition noise. If the digital outputs
must drive a load larger than 20 pF, buffering is recommended
to minimize additional noise. If the digital ASIC can accept gray
code, the AD9942 outputs can be selected to output data in gray
code format using the Control Register Bit D5. Gray coding
helps reduce potential digital transition noise compared with
binary coding.
The H1X to H4X and RG_X traces should have low inductance
to avoid excessive distortion of the signals. Heavier traces are
recommended because of the large transient current demand on
H1X to H4X from the capacitive load of the CCD. If possible,
physically locate the AD9942 closer to the CCD to reduce the
inductance on these lines. As always, the routing path should be
as direct as possible from the AD9942 to the CCD.
The CLI_X and CCDIN_X PCB traces should be carefully
matched in length and impedance to achieve optimal channel-
to-channel matching performance.
GROUNDING/DECOUPLING RECOMMENDATIONS
As Figure 30 shows, a single ground plane is recommended
for the AD9942. This ground plane should be as continuous
as possible, particularly around the P-, AI-, and A-type pins,
to ensure that all analog decoupling capacitors provide the
lowest possible impedance path between the power and bypass
pins and their respective ground pins. All high frequency
decoupling capacitors should be located as close as possible
to the package pins.
All the supply pins must be decoupled to ground with good
quality, high frequency chip capacitors. There should also be
a 4.7 μF or larger bypass capacitor for each main supply—that
is, the AVDD_X, RGVDD_X, HVDD_X, and DRVDD_X—
although this is not necessary for each individual pin. In most
applications, it is easier to share the supply for RGVDD_X and
HVDD_X, which can be done as long as the individual supply
pins are separately bypassed. A separate 3 V supply can be used
for DRVDD_X, but this supply pin should still be decoupled to
the same ground plane as the rest of the chip. A separate ground
for DRVSS_X is not recommended.
The reference bypass pins (REFT_X, REFB_X) should be
decoupled to ground as close as possible to their respective pins.
The analog input capacitor (CCDIN_X) should also be located
close to the pin.
The GND connections should be tied to the lowest impedance
ground plane on the PCB. Performance does not degrade if
several of these GND connections are left unconnected for
routing purposes.
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