
AD9942
TABLE OF CONTENTS
Features..............................................................................................1
Rev. A | Page 2 of 36
Applications.......................................................................................1
General Description.........................................................................1
Functional Block Diagram..............................................................1
Revision History...............................................................................2
Specifications.....................................................................................3
General Specifications .................................................................3
Digital Specifications ...................................................................4
Analog Specifications...................................................................5
Channel-to-Channel Specifications...........................................6
Timing Specifications ..................................................................7
Absolute Maximum Ratings............................................................8
Thermal Resistance......................................................................8
ESD Caution..................................................................................8
Pin Configuration and Function Descriptions.............................9
Terminology....................................................................................11
Equivalent Input/Output Circuits................................................12
Typical Performance Characteristics...........................................13
System Overview............................................................................14
Serial Interface Timing..................................................................15
Complete Register Listing.........................................................16
Channel A and Channel B
Precision Timing
...............................19
High Speed Timing Generation...............................................19
Timing Resolution......................................................................19
High Speed Clock Programmability........................................ 19
H Driver and RG Outputs......................................................... 21
Digital Data Outputs.................................................................. 21
Channel A and Channel B Horizontal Clamping and Blanking....22
Individual CLPOB and PBLK Sequences................................ 22
Individual HBLK Sequences..................................................... 22
Channel A and Channel B Special HBLK Patterns.................... 24
Horizontal Sequence Control................................................... 24
H-Counter Synchronization..................................................... 25
Channel A and Channel B Power-Up Procedure....................... 26
Channel A and Channel B Analog Front End Operation......... 27
DC Restore.................................................................................. 27
Correlated Double Sampler ...................................................... 27
Channel A and Channel B Variable Gain Amplifier............. 28
Channel A and Channel B ADC.............................................. 28
Channel A and Channel B CLPOB.......................................... 28
Channel A and Channel B Digital Data Outputs................... 28
Applications Information.............................................................. 29
Circuit Configuration................................................................ 29
Grounding/Decoupling Recommendations........................... 29
Driving the CLI Input................................................................ 31
Horizontal Timing Sequence Example.................................... 31
Outline Dimensions....................................................................... 33
Ordering Guide .......................................................................... 33
REVISION HISTORY
8/06—Rev. 0 to Rev. A
Changes to Table 3............................................................................ 5
Changes to Table 13........................................................................17
Change to Channel A and Channel B
Variable Gain Amplifier Section...............................................28
Updated Outline Dimensions.......................................................33
1/05—Revision 0: Initial Version