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參數資料
| 型號： | ADATE207BBP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | Quad Pin Timing Formatter |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA256 |
| 封裝： | MO-192-BAL-2, LBGA-256 |
| 文件頁數： | 27/36頁 |
| 文件大小： | 374K |
| 代理商： | ADATE207BBP |
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ADATE207
Name:
Address:
Type:
Rev. 0 | Page 27 of 36
Waveform D2 Vernier Delay and Action
0x0A
Read/Write
Table 24. Waveform D2 Vernier Delay and Action
Position
Description
Bits[15:10]
D2 Vernier Delay: The vernier delay is represented in binary by the equation,
vvvvvv × (2.5 ns/64)
Bits[09:04]
Not Used.
Bits[03:00]
D2 Action. A binary encoded data field.
0x0 = no action.
0x1 = drive low.
0x2 = drive high.
0x3 = force off.
0x4 = force on.
0x5 = force down.
0x6 = force up.
0x7 = edge compare low.
0x8 = edge compare high.
0x9 = edge compare off.
0xA = edge compare valid.
0xB = open window low.
0xC = open window high.
0xD = open window high-Z.
0xE = open window valid.
0xF = compare unknown.
Reset State
Undefined
0x00
Undefined
Name:
Address:
Type:
Waveform D2 Course Delay
0x0B
Read/Write
Table 25. Waveform D2 Course Delay
Position
Bits[15:00]
Description
D2 Course Delay. Number of 2.5 ns clock periods to count.
When this count is completed, the vernier delay (defined by the D2 vernier value programmed
into the waveform D2 vernier delay and action register) is added to the D2 course delay to
place an edge in time
Waveform D2 vernier delay and action must be written immediately before this register for the
waveform memory to be correctly written.
Reset State
Undefined
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相關代理商/技術參數 |
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| ADATE207BBPZ | 功能描述:IC TIMING FORMATTER QUAD 256BGA RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:1 系列:- 類型:時鐘/頻率發生器，多路復用器 PLL:是 主要目的:存儲器，RDRAM 輸入:晶體 輸出:LVCMOS 電路數:1 比率 - 輸入:輸出:1:2 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:Digi-Reel® 其它名稱:296-6719-6 |
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| ADATE209BBCZ | 制造商:Analog Devices 功能描述:4.0 GBPS DUAL DRIVER - Rail/Tube |
| ADATE209BCPZ | 制造商:Analog Devices 功能描述: |
| ADATE302-02 | 制造商:AD 制造商全稱:Analog Devices 功能描述:500 MHz Dual Integrated DCL with Differential Drive/Receive, Level Setting DACs, and Per Pin PMU |
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