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參數(shù)資料
| 型號： | ADE7169ACPF16-RL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | Single-Phase Energy Measurement IC with 8052 MCU, RTC and LCD driver |
| 中文描述： | ANALOG CIRCUIT, QCC64 |
| 封裝： | 9 X 9MM, MO-220VMMD, LFCSP-64 |
| 文件頁數(shù)： | 104/140頁 |
| 文件大小： | 1359K |
| 代理商： | ADE7169ACPF16-RL |
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ADE7169F16
Preliminary Technical Data
Rev. PrD | Page 104 of 140
1
0
8-Bit Autoreload Timer/Counter. TH1 holds a value that is to be reloaded into
TL1 each time it overflows.
Timer/Counter 1 Stopped.
Timer 0 Gating Control.
Set by software to enable Timer/Counter 0 only while the INT0 pin is high and the TR0 control bit
is set.
Cleared by software to enable Timer 0 whenever the TR0 control bit is set.
Timer 0 Timer or Counter Select Bit.
Set by software to the select counter operation (input from T0 pin).
Cleared by software to the select timer operation (input from internal system clock).
Timer 0 Mode Select Bits
M1
M0
Description
0
0
TH0 operates as an 8-bit timer/counter. TL0 serves as a 5-bit prescaler.
0
1
16-Bit Timer/Counter. TH0 and TL0 are cascaded; there is no prescaler.
1
0
8-Bit Autoreload Timer/Counter. TH0 holds a value that is to be reloaded into
TL0 each time it overflows.
1
1
TL0 is an 8-bit timer/counter controlled by the standard Timer 0 control bits.
TH0 is an 8-bit timer only, controlled by Timer 1 control bits.
1
1
3
Gate0
0
2
C_T0
0
1-0
T0_M1,
T0_M0
00
Table 95. Timer/Counter 0 and 1 Control SFR (TCON, 0x88)
Bit
Location
Addr.
Name
7
0x8F
TF1
Bit
Bit
Default
Value
0
Description
Timer 1 Overflow Flag.
Set by hardware on a Timer/Counter 1 overflow.
Cleared by hardware when the program counter (PC) vectors to the interrupt service
routine.
Timer 1 Run Control Bit.
Set by the user to turn on Timer/Counter 1.
Cleared by the user to turn off Timer/Counter 1.
Timer 0 Overflow Flag.
Set by hardware on a Timer/Counter 0 overflow.
Cleared by hardware when the PC vectors to the interrupt service routine.
Timer 0 Run Control Bit.
Set by the user to turn on Timer/Counter 0.
Cleared by the user to turn off Timer/Counter 0.
External Interrupt 1 (INT1) Flag.
Set by hardware by a falling edge or by a zero level applied to the external interrupt pin,
INT1, depending on the state of Bit IT1.
Cleared by hardware when the PC vectors to the interrupt service routine only if the
interrupt was transition-activated. If level-activated, the external requesting source controls
the request flag rather than the on-chip hardware.
External Interrupt 1 (IE1) Trigger Type.
Set by software to specify edge-sensitive detection, that is, 1-to-0 transition.
Cleared by software to specify level-sensitive detection, that is, zero level.
External Interrupt 0 (INT0) Flag.
Set by hardware by a falling edge or by a zero level being applied to the external interrupt
pin, INT0, depending on the statue of Bit IT0.
Cleared by hardware when the PC vectors to the interrupt service routine only if the
interrupt was transition-activated. If level-activated, the external requesting source controls
the request flag rather than the on-chip hardware.
External Interrupt 0 (IE0) Trigger Type.
Set by software to specify edge-sensitive detection, that is, 1-to-0 transition.
Cleared by software to specify level-sensitive detection, that is, zero level.
6
0x8E
TR1
0
5
0x8D
TF0
0
4
0x8C
TR0
0
3
0x8B
IE1
1
0
2
0x8A
IT1
1
0
1
0x89
IE0
1
0
0
0x88
IT0
1
0
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