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參數資料
| 型號： | ADE7169ACPF16-RL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號調理 |
| 英文描述： | Single-Phase Energy Measurement IC with 8052 MCU, RTC and LCD driver |
| 中文描述： | ANALOG CIRCUIT, QCC64 |
| 封裝： | 9 X 9MM, MO-220VMMD, LFCSP-64 |
| 文件頁數： | 89/140頁 |
| 文件大小： | 1359K |
| 代理商： | ADE7169ACPF16-RL |
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Preliminary Technical Data
ADE7169F16
Rev. PrD | Page 89 of 140
LMUX[1:0]
0
0
0
1
Reserved
2x
FP27/COM3 is used as FP27
FP28/COM2 is used as FP28
3x
FP27/COM3 is used as FP27
FP28/COM2 is used as COM2
4x
FP27/COM3 is used as COM3
FP28/COM2 is used as COM2
1
0
1
1
Table 72. LCD Configuration X SFR (LCDCONX, 0x9C)
Bit
Location
Mnemonic
7
Reserved
6
EXTRES
Bit
Default
Value
Description
0
0
Reserved
External Resistor Ladder selection bit.
0
External resistor ladder is disabled. Charge pump is enabled.
1
External resistor ladder is enabled. Charge pump is disabled.
Bias Level Selection bits. See Table 73.
5-0
BIASLVL[5:0]
0
Table 73. LCD bias voltage when contrast control is enabled
BLVL[5]
V
A
(V)
1/2 Bias
1/3 Bias
V
B
V
C
V
B
V
C
0
[
]
31
BLVL
0
:
4
BLVL
V
ref
×
1
[
]
+
×
31
0
:
4
V
ref
V
B
= V
A
V
C
= 2 x V
A
V
B
= 2 x V
A
V
C
= 3 x V
A
Table 74. LCD Configuration Y SFR (LCDCONY, 0xB1)
Bit
Location
Mnemonic
7
Reserved
6
INV_LVL
Bit
Default
Value
Description
0
0
This bit should be kept cleared for proper operation
Frame Inversion Mode Enable bit
If this bit is set, frames are inverted every other frame
If this bit is cleared, frames are not inverted
These bits should be kept cleared for proper operation
5-2
Reserved
0
1
UPDATEOVER
0
Update finished flag bit. This bit is updated by LCD driver.
When set, indicates that the LCD memory has been updated and a new
frame has begun.
Refresh LCD data memory bit, this bit should be set by user.
When set, the LCD driver does not use the data in the LCD data registers to
update display. The LCD data registers can be updated by the 8052.
When clear, the LCD driver will use the data in the LCD data registers to
update display at the next frame.
0
REFRESH
0
Table 75. LCD Clock SFR (LCDCLK, 0x96)
Bit
Location
Mnemonic
Bit
Default
Value
Description
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