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| 型號(hào)： | ADE7169ACPF16-RL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號(hào)調(diào)理 |
| 英文描述： | Single-Phase Energy Measurement IC with 8052 MCU, RTC and LCD driver |
| 中文描述： | ANALOG CIRCUIT, QCC64 |
| 封裝： | 9 X 9MM, MO-220VMMD, LFCSP-64 |
| 文件頁(yè)數(shù)： | 131/140頁(yè) |
| 文件大小： | 1359K |
| 代理商： | ADE7169ACPF16-RL |
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Preliminary Technical Data
ADE7169F16
whether a read or write operation is performed on the slave device. During the read operation, the master acknowledges are generated
automatically by the I2C peripheral. The master generated NACK before the end of a read operation is also generated automatically after
I2CRCT[4:0] bytes have been read from the slave. If the I2CADR register is updated during a transmission, instead of generating a STOP
at the end of the read or write operation, the master will generate a START condition and continue with the next communication.
Rev. PrD | Page 131 of 140
MASTER
SCL
SDA
MASTER
SLAVE
ACK BY
DATA BYFRAME 2
Figure 85: I2C Read operation
SERIAL BFRAME 1
A6
1
9
9
1
A5
A4
A3
A2
A1
A0
D6
D5
D4
D3
D2
D1
D0
R/W
D7
MASTER
DATA BFRAME N+1
9
1
D6
D5
D4
D3
D2
D1
D0
D7
SCL
SDA
MASTER
SLAVE
SLAVE
DATA BYTFRAME 2
SERIAL BFRAME 1
A6
1
9
9
1
A5
A4
A3
A2
A1
A0
D6
D5
D4
D3
D2
D1
D0
MASTER
R/W
D7
Figure 86: I2C Write operation
I2C RECEIVE AND TRANSMIT FIFOS
The I2C peripheral has a four byte receive FIFO and a four byte
transmit FIFO. The buffers reduce the overhead associated with
using the I2C peripheral. Figure 87 shows the operation of the
I2C receive and transmit FIFOs.
The TX FIFO can be loaded with four bytes to be transmitted to
the slave at the beginning of a write operation. When the
transmit FIFO is empty, the I2C transmit interrupt flag will be
set and the PC will vector to the I2C interrupt vector if this
interrupt is enabled. If a new byte is not loaded into the TX
FIFO before it is needed in the transmit shift register, the
communication will stop. An error such as not receiving an
acknowledge will also cause the communication to terminate.
In case of an error during a write operation, the TX FIFO will
be flushed.
The RX FIFO allows four bytes to be read in from the slave
before the MCU has to read the data. A receive interrupt can be
generated after each byte is received or when the RX FIFO is
full. If the peripheral is reading from a slave address, the
communication will stop once the number of received bytes
equals the number set in the I2CRCT[4:0] bits. An error such as
not receiving an acknowledge will also cause the
communication to terminate.
I2CTX
TXDATA3
TXDATA2
TXDATA1
TRANSMIT SHIFT REGISTER
4 Byte FIFO
MOV I2CTX, TXDATA3
MOV I2CTX, TXDATA4
MOV I2CTX, TXDATA1
MOV I2CTX, TXDATA2
Code to fill TX FIFO:
I2CRX
RXDATA1
RXDATA2
RXDATA3
RXDATA4
RECEIVE SHIFT REGISTER
4 Byte FIFO
MOV A, I2CRX
MOV A, I2CRX
MOV A, I2CRX
MOV A, I2CRX
; Result: A=RXDATA1
; Result: A=RXDATA2
; Result: A=RXDATA3
; Result: A=RXDATA4
Code to read RX FIFO:
TXDATA4
Figure 87: I2C FIFO operation
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