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參數資料
| 型號： | ADE7169ACPF16-RL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號調理 |
| 英文描述： | Single-Phase Energy Measurement IC with 8052 MCU, RTC and LCD driver |
| 中文描述： | ANALOG CIRCUIT, QCC64 |
| 封裝： | 9 X 9MM, MO-220VMMD, LFCSP-64 |
| 文件頁數： | 124/140頁 |
| 文件大小： | 1359K |
| 代理商： | ADE7169ACPF16-RL |
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ADE7169F16
Preliminary Technical Data
Rev. PrD | Page 124 of 140
When this bit is set to logic one, the SS pin is defined as the Slave Select input pin
for the SPI slave interface
Receive buffer overflow write enable
0
If the SPIRX SFR has not been read when a new data byte is
received, the new byte will be discarded.
1
If the SPIRX SFR has not been read when a new data byte is
received, the new byte will overwrite the old data.
Master Mode: SPI SCLK frequency
[1:0]
00
F
core
/ 8 = 512kHz if F
core
= 4.096MHz
01
F
core
/ 16 = 256kHz if F
core
= 4.096MHz
10
F
core
/ 32 = 128kHz if F
core
= 4.096MHz
11
F
core
/ 64 = 64kHz if F
core
= 4.096MHz
0xEA
2
RxOFW
0
1-0
0xE9 –
0xE8
SPIR[1:0]
0
Table 125. SPI Configuration Register SFR (SPIMOD2, 0xE9)
Bit
Location
Mnemonic
7
SPICONT
Bit
Default
Value
Description
Master Mode: SPI continuous transfer mode enable bit
0
The SPI interface will stop after one byte is transferred and SS will
be deasserted. A new data transfer can be intiated after a stalled
period.
1
The SPI interface will continue transferring data until no valid data is
availbale in the SPITx SFR. SS will remain asserted until SPITx SFR
and the transmit shift register is empty.
SPI interface enable bit
0
The SPI interface is disabled.
1
The SPI interface is enabled
SPI Open Drain Outputs configuration bit
0
Internal pull-up resistors are connected to the SPI outputs
0
6
SPIEN
0
5
SPIODO
0
1
The SPI outputs are open-drain and need external pull-up resistors
SPI Master Mode enable bit
0
The SPI interface is defined as a Slave
4
SPIMS_b
0
1
The SPI interface is defined as a Master
SPI clock polarity configuration bit – see Figure 84.
0
The default state of SCLK is low and the first SCLK edge is rising.
Depending on SPICPHA bit, the SPI data output changes state on
the falling or rising edge of SCLK while the SPI data input is sampled
on the rising or falling edge of SCLK.
The default state of SCLK is high and the first SCLK edge is falling.
Depending on SPICPHA bit, the SPI data output changes state on
the rising or falling edge of SCLK while the SPI data input is sampled
on the falling or rising edge of SCLK.
SPI clock phase configuration bit – see Figure 84.
0
The SPI data output changes state when SS goes low, at the second
edge of SCLK and then every two subsequent edges while the SPI
data input is sampled at the first SCLK edge and then every two
subsequent edges.
1
The SPI data output changes state at the first edge of SCLK and then
every two subsequent edges while the SPI data input is sampled at
the second SCLK edge and then every two subsequent edges.
Master Mode: LSB first configuration bit
3
SPICPOL
0
1
2
SPICPHA
0
1
SPILSBF
0
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