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參數資料
| 型號： | ADE7169ACPF16-RL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號調理 |
| 英文描述： | Single-Phase Energy Measurement IC with 8052 MCU, RTC and LCD driver |
| 中文描述： | ANALOG CIRCUIT, QCC64 |
| 封裝： | 9 X 9MM, MO-220VMMD, LFCSP-64 |
| 文件頁數： | 106/140頁 |
| 文件大小： | 1359K |
| 代理商： | ADE7169ACPF16-RL |
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ADE7169F16
Preliminary Technical Data
Table 101. Timer 2 High byte SFR (TH2, 0xCD)
Bit Location
Bit Mnemonic
Rev. PrD | Page 106 of 140
Default
Value
0
Description
7-0
TH2
Timer 2 Data high byte
Table 102. Timer 2 Low byte SFR (TL2, 0xCC)
Bit Location
Bit Mnemonic
Default
Value
0
Description
7-0
TL2
Timer 2 Data high byte
Table 103. Timer 2 Reload/capture High byte SFR (RACP2H, 0xCB)
Bit Location
Bit Mnemonic
Default
Value
0
Description
7-0
TH2
Timer 2 Reload/capture high byte
Table 104. Timer 2 Reload/capture Low byte SFR (RACP2L, 0xCA)
Bit Location
Bit Mnemonic
Default
Value
0
Description
7-0
TL2
Timer 2 Reload/capture low byte
TIMER 0 AND TIMER 1
Timer/Counter 0 and 1 Data Registers
Each timer consists of two 8-bit registers: Timer 0 High byte
SFR (TH0, 0x8C), Timer 0 Low byte SFR (TL0, 0x8A), Timer 1
High byte SFR (TH1, 0x8D) and Timer 1 Low byte SFR (TL1,
0x8B) These can be used as independent registers or combined
into a single 16-bit register, depending on the timers’ mode
configuration – see Table 97 to Table 100.
Timer/Counter 0 and 1 Operating Modes
This section describes the operating modes for Timer/Counters
0 and 1. Unless otherwise noted, these modes of operation are
the same for both Timer 0 and Timer 1.
Mode 0 (13-Bit Timer/Counter)
Mode 0 configures an 8-bit timer/counter. Figure 69 shows
Mode 0 operation. Note that the divide-by-12 prescaler is not
present on the single-cycle core.
0
F
CORE
CONTROL
P0.6/T0
GATE
INT0
TR0
TF0
TL0
(5 BITS)
TH0
(8 BITS)
INTERRUPT
C/T = 0
C/T = 1
Figure 69. Timer/Counter 0, Mode 0
In this mode, the timer register is configured as a 13-bit register.
As the count rolls over from all 1s to all 0s, it sets the timer
overflow flag, TF0. TF0 can then be used to request an
interrupt. The counted input is enabled to the timer when TR0
= 1 and either Gate = 0 or INT0 = 1. Setting Gate = 1 allows the
timer to be controlled by external input INT0 to facilitate pulse-
width measurements. TR0 is a control bit in the Timer/Counter
0 and 1 Control SFR (TCON, 0x88); the Gate bit is in
Timer/Counter 0 and 1 Mode SFR (TMOD, 0x89). The 13-bit
register consists of all 8 bits of Timer 0 High byte SFR (TH0,
0x8C) and the lower 5 bits of Timer 0 Low byte SFR (TL0,
0x8A). The upper 3 bits of Timer 0 Low byte SFR (TL0, 0x8A)
are indeterminate and should be ignored. Setting the run flag
(TR0) does not clear the registers.
Mode 1 (16-Bit Timer/Counter)
Mode 1 is the same as Mode 0 except that the Mode 1 timer
register runs with all 16 bits. Mode 1 is shown in Figure 70.
CONTROL
P0.6/T0
GATE
TR0
TF0
TL0
(8 BITS)
TH0
(8 BITS)
INTERRUPT
0
0
INT
C/T = 0
C/T = 1
F
CORE
Figure 70. Timer/Counter 0, Mode 1
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