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參數資料
| 型號： | ADE7169ACPF16-RL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號調理 |
| 英文描述： | Single-Phase Energy Measurement IC with 8052 MCU, RTC and LCD driver |
| 中文描述： | ANALOG CIRCUIT, QCC64 |
| 封裝： | 9 X 9MM, MO-220VMMD, LFCSP-64 |
| 文件頁數： | 113/140頁 |
| 文件大小： | 1359K |
| 代理商： | ADE7169ACPF16-RL |
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Preliminary Technical Data
ADE7169F16
Table 109. Seconds Counter SFR (SEC, 0xA3)
Bit
Location
Mnemonic
7-0
SEC
Rev. PrD | Page 113 of 140
Bit
Default
Value
Description
This counter updates every second, referenced from the calibrated 32kHz
clock. It overflows from 59 to 00, incrementing the minutes counter, MIN.
Note: This register is retained during a watchdog reset or an external reset.
It is reset after a power on reset (POR).
0
Table 110. Minutes Counter SFR (MIN, 0xA4)
Bit
Location
Mnemonic
7-0
MIN
Bit
Default
Value
Description
This counter updates every minute, referenced from the calibrated 32kHz
clock. It overflows from 59 to 00, incrementing the hours counter, HOUR.
Note: This register is retained during a watchdog reset or an external reset.
It is reset after a power on reset (POR).
0
Table 111. Hours Counter SFR (HOUR, 0xA5)
Bit
Location
Mnemonic
7-0
HOUR
Bit
Default
Value
Description
This counter updates every hour, referenced from the calibrated 32kHz
clock. If the TFH bit in the RTC Configuration SFR (TIMECON, 0xA1) is set,
the HOUR SFR overflows from 23 to 00, setting the MIDNIGHT bit and
creating a pending RTC interrupt. If the TFH bit in the RTC Configuration
SFR (TIMECON, 0xA1) is clear, the HOUR SFR overflows from 255 to 00,
setting the MIDNIGHT bit and creating a pending RTC interrupt.
Note: This register is retained during a watchdog reset or an external reset.
It is reset after a power on reset (POR).
0
Table 112. Alarm Interval SFR (INTVAL, 0xA6)
Bit
Location
Mnemonic
7-0
INTVAL
Bit
Default
Value
Description
0
The interval timer counts according to the timebase established in the
ITS[1:0] bits of the RTC Configuration SFR (TIMECON, 0xA1). Once the
number of counts is equal to INTVAL, the ALARM flag is set and a pending
RTC interrupt is created. Note that the interval counter is 8-bits so it could
count up to 255 seconds, for example.
Table 113. RTC Nominal Compensation SFR (RTCCOMP, 0xF6)
Bit
Location
Mnemonic
7-0
RTCCOMP
Bit
Default
Value
Description
The RTCCOMP SFR holds the nominal RTC compensation value at 25
°
C.
Note: This register is retained during a watchdog reset or an external reset.
It is reset after a power on reset (POR).
0
Table 114. RTC Temperature Compensation SFR (TEMPCAL, 0xF7)
Bit
Location
Mnemonic
7-0
TEMPCAL
Bit
Default
Value
Description
0
The TEMPCAL SFR is adjusted based on the temerature read in the
TEMPADC to calibrate the RTC over temperature. This allows the external
crystal shift to be compensated over temperature.
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