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參數資料
| 型號： | ADE7169ACPF16-RL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號調理 |
| 英文描述： | Single-Phase Energy Measurement IC with 8052 MCU, RTC and LCD driver |
| 中文描述： | ANALOG CIRCUIT, QCC64 |
| 封裝： | 9 X 9MM, MO-220VMMD, LFCSP-64 |
| 文件頁數： | 125/140頁 |
| 文件大小： | 1359K |
| 代理商： | ADE7169ACPF16-RL |
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Preliminary Technical Data
ADE7169F16
Rev. PrD | Page 125 of 140
0
The MSB of the SPI outputs is transmitted first
1
The LSB of the SPI outputs is transmitted first
Transfer and interrupt mode of the SPI interface.
0
Transfer is initiated when data is read from SPIRx SFR and an interrupt is
generated when there is new data in the SPIRx SFR.
0
TIMODE
0
1
Transfer is initiated when data is written to the SPITx SFR and an
interrupt is generated when the SPITx SFR is empty.
Table 126. SPI Interrupt Status Register SFR (SPISTAT, 0xEA)
Bit
Location
7
BUSY
Interrupt Flag
Default
Value
Description
SPI Peripheral Busy Flag
0
The SPI peripheral is idle
1
The SPI peripheral is busy transferring data in slave or master mode.
SPI Multi-Master Error Flag
0
A multiple master error has not occurred.
1
If the SS_EN bit is set, enabling the Slave Select input and the SS is asserted
while the SPI peripheral is transferring data as a master, then this flag is raised
to indicate the error.
SPI Receive Overflow Error Flag.
Reading the SPIRx SFR will clear this bit.
SPIR
xOF
0
X
The SPIRX register contains valid data
1
1
This bit is set if the SPIRX register is not read before the end of the
next byte transfer. If the RxOF_EN bit is set and this condition
occurs, SPIRX will be overwritten.
SPI Receive Mode Interrupt Flag.
Reading the SPIRx SFR will clear this bit.
SPIRxI
RQ
0
X
The SPIRX register does not contain new data.
1
0
This bit is set when the SPIRX register contains new data. If the
SPI/I2C interrupt is enabled, an interrupt will be generated when
this bit is set. If the SPIRX register isn’t read before the end of the
current byte transfer, the transfer will stop and the SS will be
deasserted.
1
1
The SPIRX register contains new data.
Status bit for SPI Rx buffer. When set the Rx FIFO is full. A read of the SPIRx will clear this
flag
Status bit for SPI Tx buffer. When set the Tx FIFO is underflowing and data can be write
into SPITx. A read of the SPISTAT SFR or a write to the SPITx SFR will clear this flag.
SPI Transmit Mode Interrupt Flag.
Writing new data to the SPITx SFR will clear this bit.
SPITxIRQ
TIMODE
0
X
The SPITX register is full.
1
0
The SPITX register is empty.
1
1
This bit is set when the SPITX register is empty. If the SPI/I2C
interrupt is enabled, an interrupt will be generated when
this bit is set. If new data isn’t written into the SPITX SFR
before the end of the current byte transfer, the transfer will
stop and the SS will be deasserted.
0
6
MMERR
0
TIMODE
5
SPIRxOF
0
TIMODE
4
SPIRxIRQ
0
3
SPIRxBF
0
2
SPITxUF
0
1
SPITxIRQ
0
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