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參數(shù)資料
| 型號(hào)： | ADP3180 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 6-Bit Programmable 2-, 3-, 4-Phase Synchronous Buck Controller |
| 中文描述： | 6位可編程2 - ，3 - ，4相同步降壓控制器 |
| 文件頁(yè)數(shù)： | 10/20頁(yè) |
| 文件大小： | 529K |
| 代理商： | ADP3180 |
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ADP3180
–10–
six VID inputs are changing. Additionally, the first VID change
initiates the PWRGD and CROWBAR blanking functions for a
minimum of 250 μs to prevent a false PWRGD or CROWBAR
event. Each VID change will reset the internal timer. Figure 3
shows VID on-the-fly performance when the output voltage is
stepping up and the output current is switching between mini-
mum and maximum values, which is the worst-case situation.
Figure 3. VID On-the-Fly Waveforms, Circuit of Figure 5.
VID Change = 5 mV, 5 μs per Step, 50 Steps,
I
OUT
Change = 5 A to 65 A
Power Good Monitoring
The Power Good comparator monitors the output voltage via the
CSREF pin. The PWRGD pin is an open-drain output whose
high level (when connected to a pull-up resistor) indicates that
the output voltage is within the nominal limits specified in the
Specifications table based on the VID voltage setting. PWRGD
will go low if the output voltage is outside of this specified range.
PWRGD is blanked during a VID OTF event for a period of
250 μs to prevent false signals during the time the output is
changing.
Output Crowbar
As part of the protection for the load and output components of
the supply, the PWM outputs will be driven low (turning on the
low side MOSFETs) when the output voltage exceeds the upper
Power Good threshold. This crowbar action will stop once the
output voltage has fallen below the release threshold of approxi-
mately 450 mV.
Turning on the low side MOSFETs pulls down the output as the
reverse current builds up in the inductors. If the output overvolt-
age is due to a short of the high side MOSFET, this action will
current limit the input supply or blow its fuse, protecting the
microprocessor from destruction.
Output Enable and UVLO
The input supply (VCC) to the controller must be higher than
the UVLO threshold and the EN pin must be higher than its
logic threshold for the ADP3180 to begin switching. If UVLO is
less than the threshold or the EN pin is a logic low, the ADP3180
is disabled. This holds the PWM outputs at ground, shorts the
DELAY capacitor to ground, and holds the ILIMIT pin at
ground.
In the application circuit, the ILIMIT pin should be connected
to the
OD
pins of the ADP3418 drivers. Because ILIMIT is
grounded, this disables the drivers such that both DRVH and
DRVL are grounded. This feature is important to prevent dis-
charging of the output capacitors when the controller is shut off.
If the driver outputs were not disabled, a negative voltage could
be generated on the output due to the high current discharge of
the output capacitors through the inductors.
APPLICATION INFORMATION
The design parameters for a typical Intel VRD 10 compliant
CPU application are as follows:
∑
Input voltage (V
IN
) = 12 V
∑
VID setting voltage (V
VID
) = 1.500 V
∑
Duty cycle (D) = 0.125
∑
Nominal output voltage at no load (V
ONL
) = 1.480 V
∑
Nominal output voltage at 65 A load (V
OFL
) = 1.3955 V
∑
Static output voltage drop based on a 1.3 m
W
load line (R
O
)
from no load to full load
∑
(V
D
) = V
ONL
– V
OFL
= 1.480 V – 1.3955 V = 84.5 mV
∑
Maximum Output Current (I
O
) = 65 A
∑
Maximum Output Current Step (
D
I
O
) = 60 A
∑
Number of Phases (n) = 3
∑
Switching frequency per phase (f
SW
) = 267 kHz
REV. 0
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