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參數(shù)資料
| 型號(hào)： | ADP3180 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 6-Bit Programmable 2-, 3-, 4-Phase Synchronous Buck Controller |
| 中文描述： | 6位可編程2 - ，3 - ，4相同步降壓控制器 |
| 文件頁(yè)數(shù)： | 19/20頁(yè) |
| 文件大小： | 529K |
| 代理商： | ADP3180 |
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ADP3180
–19–
LAYOUT AND COMPONENT PLACEMENT
The following guidelines are recommended for optimal perfor-
mance of a switching regulator in a PC system. Key layout issues
are illustrated in Figure 11.
12V CONNECTOR
INPUT POWER PLANE
THERMISTOR
OUTPUT
POWER
PLANE
CPU
SOCKET
KEEP-OUT
AREA
KEEP-OUT
AREA
SWITCH NODE
PLANES
KEEP-OUT
AREA
KEEP-OUT
AREA
Figure 11. Layout Recommendations
General Recommendations
∑
For good results, at least a 4-layer PCB is recommended.
This should allow the needed versatility for control circuitry
interconnections with optimal placement, power planes for
ground, input, and output power, and wide interconnection
traces in the rest of the power delivery current paths. Keep
in mind that each square unit of 1 ounce copper trace has a
resistance of ~0.53 m
W
at room temperature.
∑
Whenever high currents must be routed between PCB layers,
vias should be used liberally to create several parallel current
paths so that the resistance and inductance introduced by
these current paths is minimized and the via current rating is
not exceeded.
∑
If critical signal lines (including the output voltage sense lines
of the ADP3180) must cross through power circuitry, it is
best if a signal ground plane can be interposed between those
signal lines and the traces of the power circuitry. This serves
as a shield to minimize noise injection into the signals at the
expense of making signal ground a bit noisier.
∑
An analog ground plane should be used around and under
the ADP3180 as a reference for the components associated
with the controller. This plane should be tied to the nearest
output decoupling capacitor ground and should not be tied
to any other power circuitry to prevent power currents from
flowing in it.
∑
The components around the ADP3180 should be located
close to the controller with short traces. The most important
traces to keep short and away from other traces are the FB
and CSSUM pins. Refer to Figure 11 for more details on
layout for the CSSUM node.
∑
The output capacitors should be connected as closely as pos-
sible to the load (or connector) that receives the power (e.g.,
a microprocessor core). If the load is distributed, the capaci-
tors should also be distributed and generally in proportion to
where the load tends to be more dynamic.
∑
Avoid crossing any signal lines over the switching power path
loop, described in the Power Circuitry section.
Power Circuitry
∑
The switching power path should be routed on the PCB to
encompass the shortest possible length in order to minimize
radiated switching noise energy (i.e., EMI) and conduc-
tion losses in the board. Failure to take proper precautions
often results in EMI problems for the entire PC system as
well as noise-related operational problems in the power con-
verter control circuitry. The switching power path is the loop
formed by the current path through the input capacitors and
the power MOSFETs including all interconnecting PCB
traces and planes. The use of short and wide interconnec-
tion traces is especially critical in this path for two reasons:
it minimizes the inductance in the switching loop, which can
cause high energy ringing, and it accommodates the high cur-
rent demand with minimal voltage loss.
∑
Whenever a power dissipating component (e.g., a power
MOSFET) is soldered to a PCB, the liberal use of vias, both
directly on the mounting pad and immediately surrounding
it, is recommended. Two important reasons for this are improved
current rating through the vias and improved thermal perfor-
mance from vias extended to the opposite side of the PCB
where a plane can more readily transfer the heat to the air.
Make a mirror image of any pad being used to heatsink the
MOSFETs on the opposite side of the PCB to achieve the
best thermal dissipation to the air around the board. To fur-
ther improve thermal performance, the largest possible pad
area should be used.
∑
The output power path should also be routed to encompass a
short distance. The output power path is formed by the cur-
rent path through the inductor, the output capacitors, and
the load.
∑
For best EMI containment, a solid power ground plane
should be used as one of the inner layers extending fully
under all the power components.
Signal Circuitry
∑
The output voltage is sensed and regulated between the FB
pin and the FBRTN pin, which connects to the signal ground
at the load. To avoid differential mode noise pickup in the
sensed signal, the loop area should be small. Thus the FB and
FBRTN traces should be routed adjacent to each other atop
the power ground plane back to the controller.
∑
The feedback traces from the switch nodes should be con-
nected as close as possible to the inductor. The CSREF signal
should be connected to the output voltage at the nearest
inductor to the controller.
REV. 0
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