
ADP3180
–5–
PIN FUNCTION DESCRIPTIONS
Pin No. Mnemonic
1–6
VID4–VID0,
VID5
Function
Voltage Identification DAC Inputs. These six pins are pulled up to an internal reference, providing a logic
one if left open. When in normal operation mode, the DAC output programs the FB regulation voltage from
0.8375 V to 1.6 V. Leaving VID4 through VID0 open results in the ADP3180 going into a “No CPU” mode,
shutting off its PWM outputs.
Feedback Return. VID DAC and error amplifier reference for remote sensing of the output voltage.
Feedback Input. Error amplifier input for remote sensing of the output voltage. An external resistor between
this pin and the output voltage sets the no-load offset point.
Error Amplifier Output and Compensation Point
Power Good Output. Open-drain output that pulls to GND when the output voltage is outside of the proper
operating range.
Power Supply Enable Input. Pulling this pin to GND disables the PWM outputs.
Soft-Start Delay and Current Limit Latch-Off Delay Setting Input. An external resistor and capacitor connected
between this pin and GND set the soft-start ramp-up time and the overcurrent latch-off delay time.
Frequency Setting Resistor Input. An external resistor connected between this pin and GND sets the
oscillator frequency of the device.
PWM Ramp Current Input. An external resistor from the converter input voltage to this pin sets the
internal PWM ramp.
Current Limit Set Point/Enable Output. An external resistor from this pin to GND sets the current limit
threshold of the converter. This pin is actively pulled low when the ADP3180 EN input is low or when VCC is
below its UVLO threshold to signal to the driver IC that the driver high side and low side outputs should go low.
Current Sense Reference Voltage Input. The voltage on this pin is used as the reference for the current sense
amplifier and the Power Good and Crowbar functions. This pin should be connected to the common point
of the output inductors.
Current Sense Summing Node. External resistors from each switch node to this pin sum the average
inductor currents together to measure the total output current.
Current Sense Compensation Point. A resistor and capacitor from this pin to CSSUM determine the slope
of the load line and the positioning loop response time.
Ground. All internal biasing and the logic output signals of the device are referenced to this ground.
Current Balance Inputs. Inputs for measuring the current level in each phase. The SW pins of unused
phases should be left open.
Logic-Level PWM Outputs. Each output is connected to the input of an external MOSFET driver, such as
the ADP3413 or ADP3418. Connecting the PWM3 and/or PWM4 outputs to GND will cause that phase
to turn off, allowing the ADP3180 to operate as a 2-, 3-, or 4-phase controller.
Supply Voltage for the Device.
7
8
FBRTN
FB
9
10
COMP
PWRGD
11
12
EN
DELAY
13
RT
14
RAMPADJ
15
ILIMIT
16
CSREF
17
CSSUM
18
CSCOMP
19
20–23
GND
SW4–SW1
24–27
PWM4–
PWM1
28
VCC
REV. 0