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參數(shù)資料
| 型號(hào)： | ADP3180 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 6-Bit Programmable 2-, 3-, 4-Phase Synchronous Buck Controller |
| 中文描述： | 6位可編程2 - ，3 - ，4相同步降壓控制器 |
| 文件頁數(shù)： | 14/20頁 |
| 文件大小： | 529K |
| 代理商： | ADP3180 |
ADP3180
–14–
5. Calculate R
TH
= R
TH
R
CS
, then select the closest value of
thermistor available. Also compute a scaling factor
k
based
on the ratio of the actual thermistor value used relative to the
computed one:
k
R
R
TH ACTUAL
TH CALCULATED
=
)
)
(9)
6. Finally, calculate values for
R
CS1
and
R
CS2
using
Equation 10:
R
R
k
(
r
R
R
k
k
r
CS
CS
CS
CS
CS
CS
1
1
)
+
2
2
1
(
=
=
×
×
×
×
(
)
)
(10)
For this example,
R
CS
has been chosen to be 100 k
W
, so we start
with a thermistor value of 100 k
W
. Looking through available
0603 size thermistors, we find a Vishay
NTHS0603N01N1003JR
NTC thermistor with A = 0.3602 and B = 0.09174. From these
we compute
R
CS1
= 0.3796,
R
CS2
= 0.7195 and
R
TH
= 1.0751.
Solving for R
TH
yields 107.51 k
W
, so we choose 100 k
W
, making
k
= 0.9302. Finally, we find
R
CS1
and
R
CS2
to be 35.3 k
W
and
73.9 k
W
. Choosing the closest 1% resistor values yields a choice
of 35.7 k
W
and 73.2 k
W
.
Output Offset
Intel’s specification requires that at no load the nominal output
voltage of the regulator be offset to a lower value than the nomi-
nal voltage corresponding to the VID code. The offset is set by a
constant current source flowing out of the FB pin (
I
FB
) and flow-
ing through
R
B
. The value of
R
B
can be found using Equation 11:
R
V
V
I
V
R
V
A
k
B
VID
ONL
FB
B
=
=
=
1 5
.
1 480
.
μ
15
1 33
.
(11)
The closest standard 1% resistor value is 1.33 k
W
.
C
OUT
Selection
The required output decoupling for the regulator is typically
recommended by Intel for various processors and platforms. One
can also use some simple design guidelines to determine what
is required. These guidelines are based on having both bulk and
ceramic capacitors in the system.
The first thing is to select the total amount of ceramic capaci-
tance. This is based on the number and type of capacitor to be
used. The best location for ceramics is inside the socket, with 12
to 18 of size 1206 being the physical limit. Others can be placed
along the outer edge of the socket as well.
Combined ceramic values of 200 μF–300 μF are recommended,
usually made up of multiple 10 μF or 22 μF capacitors. Select the
number of ceramics and find the total ceramic capacitance (
C
Z
).
Next, there is an upper limit imposed on the total amount of bulk
capacitance (
C
X
) when one considers the VID on-the-fly voltage
stepping of the output (voltage step
V
V
in time
t
V
with error of
V
ERR
) and a lower limit based on meeting the critical capacitance
for load release for a given maximum load step
D
I
O
:
C
L
I
n
R
V
C
X MIN
O
O
VID
Z
)
≥
×
×
×
(12)
C
L
nK R
V
V
t
V
V
nKR
L
C
K
V
V
X MAX
O
V
VID
V
VID
V
O
Z
VERR
V
)
≤
×
×
+
×
=
2
2
1
1
where
ln
(13)
To meet the conditions of these expressions and transient
response, the ESR of the bulk capacitor bank (R
X
) should be less
than two times the droop resistance, R
O
. If the C
X(MIN)
is larger
than C
X(MAX)
, the system will not meet the VID on-the-fly speci-
fication and may require the use of a smaller inductor or more
phases (and may have to increase the switching frequency to keep
the output ripple the same).
For our example, 23 10 μF 1206 MLC capacitors (C
Z
= 230 μF)
were used. The VID on-the-fly step change is 250 mV in 150 μs
with a setting error of 2.5 mV. Solving for the bulk capacitance
yields:
C
nH
m
A
.
V
F
mF
C
nH
×
1 3
mV
×
m
V
s
V
mV
m
nH
X MIN
X MAX
)
)
≥
×
×
×
=
≤
×
×
×
+
×
250
×
×
×
×
600
3 1 3
60
1 5
230
5 92
.
600
4 6
.
250
3
1 5
.
1
150
1 5
.
3
4 6
.
1 3
.
600
2
2
.
)
μ
μ
=
where
Using eight 820 μF A1-Polys with a typical ESR of 8 m
W,
each
yields C
X
= 6.56 mF with an R
X
= 1.0 m
W.
One last check should be made to ensure that the ESL of the
bulk capacitors (L
X
) is low enough to limit the initial high fre-
quency transient spike. This is tested using:
=
2
1
230
23 9
4 6
.
μ
F
mF
K
.
L
C
R
L
F
m
pH
X
Z
O
X
≤
×
≤
×
=
2
2
230
1 3
389
μ
)
(14)
In this example,
L
X
is 375 pH for the eight A1-Polys capacitors,
which satisfies this limitation. If the L
X
of the chosen bulk capaci-
tor bank is too large, the number of capacitors must be increased.
One should note for this multimode control technique, all
ceramic designs can be used as long as the conditions of
Equations 11, 12, and 13 are satisfied.
Power MOSFETs
For this example, the N-channel power MOSFETs have been
selected for one high side switch and two low side switches per
phase. The main selection parameters for the power MOSFETs
are V
GS(TH)
, Q
G
, C
ISS
, C
RSS
, and R
DS(ON)
. The minimum gate drive
voltage (the supply voltage to the ADP3418) dictates whether
standard threshold or logic-level threshold MOSFETs must be
used. With V
GATE
~10 V, logic-level threshold MOSFETs (V
GS(TH)
< 2.5 V) are recommended.
The maximum output current I
O
determines the R
DS(ON)
requirement for the low side (synchronous) MOSFETs. With
the ADP3180, currents are balanced between phases, thus the
current in each low side MOSFET is the output current divided
by the total number of MOSFETs (
n
SF
). With conduction losses
REV. 0
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