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參數(shù)資料
| 型號(hào)： | ADP3180 |
| 廠(chǎng)商： | Analog Devices, Inc. |
| 英文描述： | 6-Bit Programmable 2-, 3-, 4-Phase Synchronous Buck Controller |
| 中文描述： | 6位可編程2 - ，3 - ，4相同步降壓控制器 |
| 文件頁(yè)數(shù)： | 8/20頁(yè) |
| 文件大小： | 529K |
| 代理商： | ADP3180 |
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ADP3180
–8–
The PWM outputs become logic-level devices once normal
operation starts. The detection is normal and is intended for driv-
ing external gate drivers, such as the ADP3418. Since each phase
is monitored independently, operation approaching 100% duty
cycle is possible. Also, more than one output can be on at a time
for overlapping phases.
Master Clock Frequency
The clock frequency of the ADP3180 is set with an external
resistor connected from the RT pin to ground. The frequency fol-
lows the graph in TPC 1. To determine the frequency per phase,
the clock is divided by the number of phases in use. If PWM4 is
grounded, divide the master clock by 3 for the frequency of the
remaining phases. If PWM3 and PWM4 are grounded, divide by 2.
If all phases are in use, divide by 4.
Output Voltage Differential Sensing
The ADP3180 combines differential sensing with a high accuracy
VID DAC and reference and a low offset error amplifier to main-
tain a worst-case specification of ±10 mV differential sensing
error with a VID input of 1.6000 V over its full operating output
voltage and temperature range. The output voltage is sensed between
the FB and FBRTN pins. FB should be connected through a
resistor to the regulation point, usually the remote sense pin of
the microprocessor. FBRTN should be connected directly to the
remote sense ground point. The internal VID DAC and precision
reference are referenced to FBRTN, which has a minimal current
of 90 μA to allow accurate remote sensing. The internal error
amplifier compares the output of the DAC to the FB pin to regu-
late the output voltage.
Output Current Sensing
The ADP3180 provides a dedicated current sense amplifier
(CSA) to monitor the total output current for proper voltage
positioning versus load current and for current limit detection.
Sensing the load current at the output gives the total average
current being delivered to the load, which is an inherently more
accurate method than peak current detection or sampling the
current across a sense element such as the low side MOSFET.
This amplifier can be configured several ways, depending on the
objectives of the system:
∑
Output inductor ESR sensing without thermistor for lowest cost
∑
Output inductor ESR sensing with thermistor for improved
accuracy with tracking of inductor temperature
∑
Sense resistors for highest accuracy measurements
The positive input of the CSA is connected to the CSREF pin,
which is connected to the output voltage. The inputs to the
amplifier are summed together through resistors from the sensing
element (such as the switch node side of the output inductors)
to the inverting input, CSSUM. The feedback resistor between
CSCOMP and CSSUM sets the gain of the amplifier, and a filter
capacitor is placed in parallel with this resistor. The gain of the
amplifier is programmable by adjusting the feedback resistor to
set the load line required by the microprocessor. The current
information is then given as the difference of CSREF – CSCOMP.
This difference signal is used internally to offset the VID DAC
for voltage positioning and as a differential input for the current
limit comparator.
To provide the best accuracy for the sensing of current, the CSA
has been designed to have a low offset input voltage. Also, the
sensing gain is determined by external resistors so that it can be
made extremely accurate.
Active Impedance Control Mode
For controlling the dynamic output voltage droop as a function
of output current, a signal proportional to the total output cur-
rent at the CSCOMP pin can be scaled to be equal to the droop
impedance of the regulator times the output current. This droop
voltage is then used to set the input control voltage to the system.
The droop voltage is subtracted from the DAC reference input
voltage directly to tell the error amplifier where the output volt-
age should be. This differs from previous implementations and
allows enhanced feed-forward response.
Current Control Mode and Thermal Balance
The ADP3180 has individual inputs that are used for monitoring
the current in each phase. This information is combined with an
internal ramp to create a current balancing feedback system that
has been optimized for initial current balance accuracy and
dynamic thermal balancing during operation. This current bal-
ance information is independent of the average output current
information used for positioning described previously.
The magnitude of the internal ramp can be set to optimize the
transient response of the system. It also monitors the supply volt-
age for feed-forward control for changes in the supply. A
resistor connected from the power input voltage to the
RAMPADJ pin determines the slope of the internal PWM ramp.
Detailed information about programming the ramp is given in
the Application Information section.
External resistors can be placed in series with individual phases
to create an intentional current imbalance if desired, such as
when one phase may have better cooling and can support higher
currents. Resistors R
SW1
through R
SW4
(see the typical application
circuit in Figure 4) can be used for adjusting thermal balance. It
is best to have the ability to add these resistors during the initial
design, so make sure placeholders are provided in the layout.
To increase the current in any given phase, make R
SW
for that
phase larger (make R
SW
= 0 for the hottest phase and do not
change during balancing). Increasing R
SW
to only 500
W
will
make a substantial increase in phase current. Increase each R
SW
value by small amounts to achieve balance, starting with the cool-
est phase first.
Voltage Control Mode
A high gain-bandwidth voltage mode error amplifier is used for
the voltage-mode control loop. The control input voltage to the
positive input is set via the VID 6-bit logic code according to the
voltages listed in Table I. This voltage is also offset by the droop
voltage for active positioning of the output voltage as a function
of current, commonly known as active voltage positioning. The
output of the amplifier is the COMP pin, which sets the termina-
tion voltage for the internal PWM ramps.
The negative input (FB) is tied to the output sense location with
a resistor R
B
and is used for sensing and controlling the output
voltage at this point. A current source from the FB pin flowing
through R
B
is used for setting the no-load offset voltage from the
VID voltage. The no-load voltage will be negative with respect to
the VID DAC. The main loop compensation is incorporated into
the feedback network between FB and COMP.
Soft-Start
The power-on ramp up time of the output voltage is set with a
capacitor and resistor in parallel from the DELAY pin to ground.
The RC time constant also determines the current limit latch-off
time as explained in the following section. In UVLO or when
REV. 0
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