
ADP3180
–7–
VID4
VID3
VID2
VID1
VID0
VID5
V
OUT(NOM)
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
0
0
1
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
0
0
1
1
0
0
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
No CPU
0.8375 V
0.850 V
0.8625 V
0.875 V
0.8875 V
0.900 V
0.9125 V
0.925 V
0.9375 V
0.950 V
0.9625 V
0.975 V
0.9875 V
1.000 V
1.0125 V
1.025 V
1.0375 V
1.050 V
1.0625 V
1.075 V
1.0875 V
1.100 V
1.1125 V
1.125 V
1.1375 V
1.150 V
1.1625 V
1.175 V
1.1875 V
1.200 V
1.2125 V
VID4
VID3
VID2
VID1
VID0
VID5
V
OUT(NOM)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1.225 V
1.2375 V
1.250 V
1.2625 V
1.275 V
1.2875 V
1.300 V
1.3125 V
1.325 V
1.3375 V
1.350 V
1.3625 V
1.375 V
1.3875 V
1.400 V
1.4125 V
1.425 V
1.4375 V
1.450 V
1.4625 V
1.475 V
1.4875 V
1.500 V
1.5125 V
1.525 V
1.5375 V
1.550 V
1.5625 V
1.575 V
1.5875 V
1.600 V
X = Don't Care
Table I. Output Voltage vs. VID Code
THEORY OF OPERATION
The ADP3180 combines a multimode, fixed frequency PWM
control with multiphase logic outputs for use in 2-, 3-, and
4-phase synchronous buck CPU core supply power converters.
The internal 6-bit VID DAC conforms to Intel’s VRD/VRM 10
specifications. Multiphase operation is important for produc-
ing the high currents and low voltages demanded by today’s
microprocessors. Handling the high currents in a single-phase
converter would place high thermal demands on the components
in the system such as the inductors and MOSFETs.
The multimode control of the ADP3180 ensures a stable, high
performance topology for:
∑
Balancing currents and thermals between phases
∑
High speed response at the lowest possible switching frequency
and output decoupling
∑
Minimizing thermal switching losses due to lower frequency
operation
∑
Tight load line regulation and accuracy
∑
High current output from having up to 4-phase operation
∑
Reduced output ripple due to multiphase cancellation
∑
PC board layout noise immunity
∑
Ease of use and design due to independent component selection
∑
Flexibility in operation for tailoring design to low cost or high
performance
Number of Phases
The number of operational phases and their phase relationship
is determined by the internal circuitry that monitors the PWM
outputs. Normally, the ADP3180 operates as a 4-phase PWM
controller. Grounding the PWM4 pin programs 3-phase opera-
tion, and grounding the PWM3 and PWM4 pins programs
2-phase operation.
When the ADP3180 is enabled, the controller outputs a voltage
on PWM3 and PWM4 that is approximately 550 mV. An inter-
nal comparator checks each pin’s voltage versus a threshold of
400 mV. If the pin is grounded, then it will be below the thresh-
old and the phase will be disabled. The output resitance of the
PWM pin is approximately 5 k
W
during this detection time. Any
external pull-down resistance connected to the PWM pin should
not be less than 25 k
W
to ensure proper operation. The phase
detection is made during the first two clock cycles of the internal
oscillator. After this time, if the PWM output was not grounded,
the 5 k
W
resistance is removed and will switch between 0 V and
5 V. If the PWM output was grounded, it will remain off.
REV. 0