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參數資料
| 型號： | ADP3180 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 6-Bit Programmable 2-, 3-, 4-Phase Synchronous Buck Controller |
| 中文描述： | 6位可編程2 - ，3 - ，4相同步降壓控制器 |
| 文件頁數： | 17/20頁 |
| 文件大?。?/td> | 529K |
| 代理商： | ADP3180 |
ADP3180
–17–
R
T
C
s
pF
k
A
C
A
=
=
=
6 2
371
16 7
.
.
μ
(31)
C
T
R
s
k
n
B
B
B
=
=
=
1 97
1 33
.
1 48
.
.
F
μ
(32)
C
T
R
ns
k
p
FB
D
A
=
=
=
521
1.
31 2
F
.
(33)
Choosing the closest standard values for these components yields:
C
A
= 390 pF,
R
A
= 16.9 k
W
,
C
B
= 1.5 nF, and
C
FB
= 33 pF.
Figure 6 shows the typical transient response using the compen-
sation values.
Figure 6. Typical Transient Response for Design Example
C
IN
Selection and Input Current di/dt Reduction
In continuous inductor-current mode, the source current of the
high side MOSFET is approximately a square wave with a duty
ratio equal to n V
OUT
/V
IN
and an amplitude of one-nth of the
maximum output current. To prevent large voltage transients,
a low ESR input capacitor sized for the maximum rms current
must be used. The maximum rms capacitor current is given by:
I
D
I
N
D
I
A
A
CRMS
O
CRMS
=
×
×
×
=
×
×
=
1
1
0 125 65
.
1
0 125
.
3
1
10 5
.
(34)
Note that the capacitor manufacturer’s ripple current ratings are
often based on only 2,000 hours of life. This makes it advisable
to further derate the capacitor or to choose a capacitor rated at
a higher temperature than required. Several capacitors may be
placed in parallel to meet size or height requirements in the
design. In this example, the input capacitor bank is formed by
three 2200 μF, 16 V Nichicon capacitors with a ripple current
rating of 3.5 A each.
To reduce the input-current di/dt to below the recommended
maximum of 0.1 A/μs, an additional small inductor (L > 1 μH @
15 A) should be inserted between the converter and the supply
bus. That inductor also acts as a filter between the converter and
the primary power source.
(
(
R
R
V
V
V
V
CS
NEW
CS
OLD
NL
FLCOLD
NL
FLHOT
2
2
(
)
(
)
=
×
)
)
(35)
0
10
20
OUTPUT CURRENT – A
30
40
50
60
100
80
60
40
20
0
E
Figure 7. Efficiency of the Circuit of Figure 4
vs. Output Current
TUNING PROCEDURE FOR THE ADP3180
1. Build circuit based on compensation values computed from
design spreadsheet.
2. Hook up dc load to circuit, turn on and verify operation.
Also check for jitter at no-load and full-load.
DC Loadline Setting
3. Measure output voltage at no-load (V
NL
). Verify it is within
tolerance.
4. Measure output voltage at full-load cold (V
FLCOLD
). Let
board set for ~10 minutes at full-load and measure output
(V
FLHOT
). If there is a change of more than a couple of mil-
livolts, adjust R
CS1
and R
CS2
using Equations 35 and 37.
5. Repeat Step 4 until cold and hot voltage measurements
remain the same.
6. Measure output voltage from no-load to full-load using 5 A
steps. Compute the loadline slope for each change and then
average to get overall loadline slope (
R
OMEAS
).
7. If
R
OMEAS
is off from
R
O
by more than 0.05 m
W
, use the fol-
lowing to adjust the
R
PH
values:
R
R
R
R
PH NEW
PH OLD
OMEAS
O
)
)
=
×
(36)
8. Repeat Steps 6 and 7 to check loadline and repeat adjust-
ments if necessary.
9. Once complete with dc loadline adjustment, do not change
R
PH
, R
CS1
, R
CS2
, or R
TH
for rest of procedure.
R
R
R
R
R
R
R
R
R
R
CS
NEW
CS OLD
1
TH
C
CS OLD
1
TH
C
CS
OLD
CS
NEW
CS OLD
1
TH
C
TH
C
2
25
25
2
2
25
25
1
1
(
)
)
°
(
)
)
°
(
)
(
)
(
)
)
°
(
)
°
(
)
=
+
×
+
(
)
×
(
)
(37)
REV. 0
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