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參數資料
| 型號： | ADSP-21161N |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 數字信號處理 |
| 英文描述： | DSP Microcomputer |
| 中文描述： | DSP微機 |
| 文件頁數： | 7/60頁 |
| 文件大小： | 1019K |
| 代理商： | ADSP-21161N |
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–7–
REV. A
ADSP-21161N
synchronous approach, coupled with the core clock frequency,
supports data transfer at a high throughput—up to 400 M bytes/s
for 32-bit transfers and 600 M bytes/s for 48-bit transfers.
The SDRAM interface provides a glueless interface with
standard SDRAMs—16 Mb, 64 Mb, 128 Mb, and 256 Mb—
and includes options to support additional buffers between the
ADSP-21161N and SDRAM. The SDRAM interface is
extremely flexible and provides capability for connecting
SDRAMs to any one of the ADSP-21161N’s four external
memory banks, with up to all four banks mapped to SDRAM.
Systems with several SDRAM devices connected in parallel may
require buffering to meet overall system timing requirements.
The ADSP-21161N supports pipelining of the address and
control signals to enable such buffering between itself and
multiple SDRAM devices.
Target Board JTAG Emulator Connector
Analog Devices DSP Tools product line of JTAG emulators uses
the IEEE 1149.1 JTAG test access port of the ADSP-21161N
processor to monitor and control the target board processor
during emulation. Analog Devices DSP Tools product line of
JTAG emulators provides emulation at full processor speed,
allowing inspection and modification of memory, registers, and
processor stacks. The processor’s JTAG interface ensures that the
emulator will not affect target system loading or timing.
For complete information on SHARC Analog Devices DSP
Tools product line of JTAG emulator operation, see the appro-
priate Emulator Hardware User’s Guide. For detailed infor-
mation on the interfacing of Analog Devices JTAG emulators
with Analog Devices DSP products with JTAG emulation ports,
please refer to Engineer to Engineer Note
EE-68: Analog Devices
JTAG Emulation Technical Reference
. Both of these documents can
be found on the Analog Devices website:
DMA ControllerThe ADSP-21161N’s on-chip DMA controller enables zero-
overhead data transfers without processor intervention. The
DMA controller operates independently and invisibly to the
processor core, allowing DMA operations to occur while the core
is simultaneously executing its program instructions. DMA
transfers can occur between the ADSP-21161N’s internal
memory and external memory, external peripherals, or a host
processor. DMA transfers can also occur between the ADSP-
21161N’s internal memory and its serial ports, link ports, or the
SPI-compatible (Serial Peripheral Interface) port. External bus
packing and unpacking of 32-, 48-, or 64-bit words in internal
memory is performed during DMA transfers from either 8-,
16-, or 32-bit wide external memory. Fourteen channels of DMA
are available on the ADSP-21161N—two are shared between the
SPI interface and the link ports, eight via the serial ports, and
four via the processor’s external port (for host processor, other
ADSP-21161Ns, memory, or I/O transfers). Programs can be
downloaded to the ADSP-21161N using DMA transfers. Asyn-
chronous off-chip peripherals can control two DMA channels
using DMA Request/Grant lines (
DMAR2–1
,
DMAG2–1
).
Other DMA features include interrupt generation upon comple-
tion of DMA transfers, and DMA chaining for automatic linked
DMA transfers.
Multiprocessing
The ADSP-21161N offers powerful features tailored to
multiprocessing DSP systems. The external port and link ports
provide integrated glueless multiprocessing support.
The external port supports a unified address space (see
Figure 2
on Page 6
) that enables direct interprocessor accesses of each
ADSP-21161N’s internal memory-mapped (I/O processor) reg-
isters. All other internal memory can be indirectly accessed via
DMA transfers initiated via the programming of the IOP DMA
parameter and control registers. Distributed bus arbitration logic
is included on-chip for simple, glueless connection of systems
containing up to six ADSP-21161Ns and a host processor.
Master processor change over incurs only one cycle of overhead.
Bus arbitration is selectable as either fixed or rotating priority.
Bus lock enables indivisible read-modify-write sequences for
semaphores. A vector interrupt is provided for interprocessor
commands. Maximum throughput for interprocessor data
transfer is 400 M bytes/s over the external port.
Two link ports provide a second method of multiprocessing com-
munications. Each link port can support communications to
another ADSP-21161N. The ADSP-21161N, running at
100 MHz, has a maximum throughput for interprocessor com-
munications over the links of 200 M bytes/s. The link ports and
cluster multiprocessing can be used concurrently or
independently.
Link Ports
The ADSP-21161N features two 8-bit link ports that provide
additional I/O capabilities. With the capability of running at
100 MHz, each link port can support 100 M bytes/s. Link port
I/O is especially useful for point-to-point interprocessor commu-
nication in multiprocessing systems. The link ports can operate
independently and simultaneously, with a maximum data
throughput of 200 M bytes/s. Link port data is packed into
48- or 32-bit words and can be directly read by the core processor
Figure 3. External Data Alignment Options
DATA15–0
15
8 7
0
L1DATA7–0
DATA15-8
L0DATA7–0
DATA7–0
16-BIT PACKED DMA DATA
16-BIT PACKED INSTRUC-
TION EXECUTION
FLOAT OR FIXED, D31–D0,
32-BIT PACKED
32-BIT PACKED INSTRUC-
TION
EXTRA DATA LINES DATA15–0 ARE ONLY ACCESSIBLE IF LINK PORTS
ARE DISABLED. ENABLE THESE ADDITIONAL DATA LINKS BY SELECT-
ING IPACK1–0 = 01 IN SYSCON.
48-BIT INSTRUCTION FETCH
(NO PACKING)
47
40 39
32 31
24 23
16
DATA47–16
8-BIT PACKED DMA DATA
8-BIT PACKED INSTRUCTION
EXECUTION
PROM
BOOT
NOTE:
相關PDF資料 |
PDF描述 |
|---|---|
| ADSP-21161NCCA-100 | DSP Microcomputer |
| ADSP-21161NKCA-100 | DSP Microcomputer |
| ADSP-21262SBBC-150 | Embedded Processor |
| ADSP-21262SBBCZ150 | Embedded Processor |
| ADSP-21262SKSTZ200 | SHARC Processor |
相關代理商/技術參數 |
參數描述 |
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| ADSP-21161NCCA-100 | 功能描述:IC DSP CONTROLLER 32BIT 225MBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數字式信號處理器） 系列:SHARC® 標準包裝:2 系列:StarCore 類型:SC140 內核 接口:DSI，以太網，RS-232 時鐘速率:400MHz 非易失內存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，FCBGA 供應商設備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-21161NCCAZ100 | 功能描述:IC DSP CONTROLLER 32BIT 225MBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數字式信號處理器） 系列:SHARC® 標準包裝:2 系列:StarCore 類型:SC140 內核 接口:DSI，以太網，RS-232 時鐘速率:400MHz 非易失內存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，FCBGA 供應商設備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-21161NKCA-100 | 功能描述:IC DSP CONTROLLER 32BIT 225MBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數字式信號處理器） 系列:SHARC® 標準包裝:2 系列:StarCore 類型:SC140 內核 接口:DSI，以太網，RS-232 時鐘速率:400MHz 非易失內存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，FCBGA 供應商設備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-21161NKCA-100Z | 制造商:Analog Devices 功能描述: |
| ADSP-21161NKCAZ100 | 功能描述:IC DSP CONTROLLER 32BIT 225MBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數字式信號處理器） 系列:SHARC® 標準包裝:2 系列:StarCore 類型:SC140 內核 接口:DSI，以太網，RS-232 時鐘速率:400MHz 非易失內存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，FCBGA 供應商設備封裝:431-FCPBGA（20x20） 包裝:托盤 |
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